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Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next

Browse Source 
This pull includes the new Arm "komeda" DRM driver. It is currently hosted
in the same repo as the other "mali-dp" driver because it is the next
iteration of the IP.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190131173600.GN25147@e110455-lin.cambridge.arm.com
This commit is contained in:
Dave Airlie
2019-02-01 09:51:23 +10:00
parent fb27a3cb9c dcc9d76b6d
commit 74b7d6a913
30 changed files with 2998 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/arm/display/Kbuild Normal file
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# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_KOMEDA) += komeda/

14
drivers/gpu/drm/arm/display/Kconfig Normal file
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# SPDX-License-Identifier: GPL-2.0
config DRM_KOMEDA
tristate "ARM Komeda display driver"
depends on DRM && OF
depends on COMMON_CLK
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
select VIDEOMODE_HELPERS
help
Choose this option if you want to compile the ARM Komeda display
Processor driver. It supports the D71 variants of the hardware.
If compiled as a module it will be called komeda.

42
drivers/gpu/drm/arm/display/include/malidp_io.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _MALIDP_IO_H_
#define _MALIDP_IO_H_
#include <linux/io.h>
static inline u32
malidp_read32(u32 __iomem *base, u32 offset)
{
return readl((base + (offset >> 2)));
}
static inline void
malidp_write32(u32 __iomem *base, u32 offset, u32 v)
{
writel(v, (base + (offset >> 2)));
}
static inline void
malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v)
{
u32 tmp = malidp_read32(base, offset);
tmp &= (~m);
malidp_write32(base, offset, v | tmp);
}
static inline void
malidp_write_group(u32 __iomem *base, u32 offset, int num, const u32 *values)
{
int i;
for (i = 0; i < num; i++)
malidp_write32(base, offset + i * 4, values[i]);
}
#endif /*_MALIDP_IO_H_*/

23
drivers/gpu/drm/arm/display/include/malidp_product.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _MALIDP_PRODUCT_H_
#define _MALIDP_PRODUCT_H_
/* Product identification */
#define MALIDP_CORE_ID(__product, __major, __minor, __status) \
((((__product) & 0xFFFF) << 16) | (((__major) & 0xF) << 12) | \
(((__minor) & 0xF) << 8) | ((__status) & 0xFF))
#define MALIDP_CORE_ID_PRODUCT_ID(__core_id) ((__u32)(__core_id) >> 16)
#define MALIDP_CORE_ID_MAJOR(__core_id) (((__u32)(__core_id) >> 12) & 0xF)
#define MALIDP_CORE_ID_MINOR(__core_id) (((__u32)(__core_id) >> 8) & 0xF)
#define MALIDP_CORE_ID_STATUS(__core_id) (((__u32)(__core_id)) & 0xFF)
/* Mali-display product IDs */
#define MALIDP_D71_PRODUCT_ID 0x0071
#endif /* _MALIDP_PRODUCT_H_ */

16
drivers/gpu/drm/arm/display/include/malidp_utils.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _MALIDP_UTILS_
#define _MALIDP_UTILS_
#define has_bit(nr, mask) (BIT(nr) & (mask))
#define has_bits(bits, mask) (((bits) & (mask)) == (bits))
#define dp_for_each_set_bit(bit, mask) \
for_each_set_bit((bit), ((unsigned long *)&(mask)), sizeof(mask) * 8)
#endif /* _MALIDP_UTILS_ */

21
drivers/gpu/drm/arm/display/komeda/Makefile Normal file
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# SPDX-License-Identifier: GPL-2.0
ccflags-y := \
-I$(src)/../include \
-I$(src)
komeda-y := \
komeda_drv.o \
komeda_dev.o \
komeda_format_caps.o \
komeda_pipeline.o \
komeda_framebuffer.o \
komeda_kms.o \
komeda_crtc.o \
komeda_plane.o \
komeda_private_obj.o
komeda-y += \
d71/d71_dev.o
obj-$(CONFIG_DRM_KOMEDA) += komeda.o

111
drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include "malidp_io.h"
#include "komeda_dev.h"
static int d71_enum_resources(struct komeda_dev *mdev)
{
/* TODO add enum resources */
return -1;
}
#define __HW_ID(__group, __format) \
((((__group) & 0x7) << 3) | ((__format) & 0x7))
#define RICH KOMEDA_FMT_RICH_LAYER
#define SIMPLE KOMEDA_FMT_SIMPLE_LAYER
#define RICH_SIMPLE (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_SIMPLE_LAYER)
#define RICH_WB (KOMEDA_FMT_RICH_LAYER | KOMEDA_FMT_WB_LAYER)
#define RICH_SIMPLE_WB (RICH_SIMPLE | KOMEDA_FMT_WB_LAYER)
#define Rot_0 DRM_MODE_ROTATE_0
#define Flip_H_V (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y | Rot_0)
#define Rot_ALL_H_V (DRM_MODE_ROTATE_MASK | Flip_H_V)
#define LYT_NM BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16)
#define LYT_WB BIT(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8)
#define LYT_NM_WB (LYT_NM | LYT_WB)
#define AFB_TH AFBC(_TILED | _SPARSE)
#define AFB_TH_SC_YTR AFBC(_TILED | _SC | _SPARSE | _YTR)
#define AFB_TH_SC_YTR_BS AFBC(_TILED | _SC | _SPARSE | _YTR | _SPLIT)
static struct komeda_format_caps d71_format_caps_table[] = {
/* HW_ID | fourcc | tile_sz | layer_types | rots | afbc_layouts | afbc_features */
/* ABGR_2101010*/
{__HW_ID(0, 0), DRM_FORMAT_ARGB2101010, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 1), DRM_FORMAT_ABGR2101010, 1, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
{__HW_ID(0, 2), DRM_FORMAT_RGBA1010102, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(0, 3), DRM_FORMAT_BGRA1010102, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* ABGR_8888*/
{__HW_ID(1, 0), DRM_FORMAT_ARGB8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 1), DRM_FORMAT_ABGR8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 1), DRM_FORMAT_ABGR8888, 1, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
{__HW_ID(1, 2), DRM_FORMAT_RGBA8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(1, 3), DRM_FORMAT_BGRA8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* XBGB_8888 */
{__HW_ID(2, 0), DRM_FORMAT_XRGB8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 1), DRM_FORMAT_XBGR8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 2), DRM_FORMAT_RGBX8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
{__HW_ID(2, 3), DRM_FORMAT_BGRX8888, 1, RICH_SIMPLE_WB, Flip_H_V, 0, 0},
/* BGR_888 */ /* none-afbc RGB888 doesn't support rotation and flip */
{__HW_ID(3, 0), DRM_FORMAT_RGB888, 1, RICH_SIMPLE_WB, Rot_0, 0, 0},
{__HW_ID(3, 1), DRM_FORMAT_BGR888, 1, RICH_SIMPLE_WB, Rot_0, 0, 0},
{__HW_ID(3, 1), DRM_FORMAT_BGR888, 1, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR_BS}, /* afbc */
/* BGR 16bpp */
{__HW_ID(4, 0), DRM_FORMAT_RGBA5551, 1, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 1), DRM_FORMAT_ABGR1555, 1, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 1), DRM_FORMAT_ABGR1555, 1, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
{__HW_ID(4, 2), DRM_FORMAT_RGB565, 1, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 3), DRM_FORMAT_BGR565, 1, RICH_SIMPLE, Flip_H_V, 0, 0},
{__HW_ID(4, 3), DRM_FORMAT_BGR565, 1, RICH_SIMPLE, Rot_ALL_H_V, LYT_NM_WB, AFB_TH_SC_YTR}, /* afbc */
{__HW_ID(4, 4), DRM_FORMAT_R8, 1, SIMPLE, Rot_0, 0, 0},
/* YUV 444/422/420 8bit */
{__HW_ID(5, 0), 0 /*XYUV8888*/, 1, 0, 0, 0, 0},
/* XYUV unsupported*/
{__HW_ID(5, 1), DRM_FORMAT_YUYV, 1, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH}, /* afbc */
{__HW_ID(5, 2), DRM_FORMAT_YUYV, 1, RICH, Flip_H_V, 0, 0},
{__HW_ID(5, 3), DRM_FORMAT_UYVY, 1, RICH, Flip_H_V, 0, 0},
{__HW_ID(5, 4), 0, /*X0L0 */ 2, 0, 0, 0}, /* Y0L0 unsupported */
{__HW_ID(5, 6), DRM_FORMAT_NV12, 1, RICH, Flip_H_V, 0, 0},
{__HW_ID(5, 6), 0/*DRM_FORMAT_YUV420_8BIT*/, 1, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH}, /* afbc */
{__HW_ID(5, 7), DRM_FORMAT_YUV420, 1, RICH, Flip_H_V, 0, 0},
/* YUV 10bit*/
{__HW_ID(6, 0), 0,/*XVYU2101010*/ 1, 0, 0, 0, 0},/* VYV30 unsupported */
{__HW_ID(6, 6), 0/*DRM_FORMAT_X0L2*/, 2, RICH, Flip_H_V, 0, 0},
{__HW_ID(6, 7), 0/*DRM_FORMAT_P010*/, 1, RICH, Flip_H_V, 0, 0},
{__HW_ID(6, 7), 0/*DRM_FORMAT_YUV420_10BIT*/, 1, RICH, Rot_ALL_H_V, LYT_NM, AFB_TH},
};
static void d71_init_fmt_tbl(struct komeda_dev *mdev)
{
struct komeda_format_caps_table *table = &mdev->fmt_tbl;
table->format_caps = d71_format_caps_table;
table->n_formats = ARRAY_SIZE(d71_format_caps_table);
}
static struct komeda_dev_funcs d71_chip_funcs = {
.init_format_table = d71_init_fmt_tbl,
.enum_resources = d71_enum_resources,
.cleanup = NULL,
};
#define GLB_ARCH_ID 0x000
#define GLB_CORE_ID 0x004
#define GLB_CORE_INFO 0x008
struct komeda_dev_funcs *
d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
{
chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
return &d71_chip_funcs;
}

106
drivers/gpu/drm/arm/display/komeda/komeda_crtc.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/pm_runtime.h>
#include "komeda_dev.h"
#include "komeda_kms.h"
struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
};
static const struct drm_crtc_funcs komeda_crtc_funcs = {
};
int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
struct komeda_dev *mdev)
{
struct komeda_crtc *crtc;
struct komeda_pipeline *master;
char str[16];
int i;
kms->n_crtcs = 0;
for (i = 0; i < mdev->n_pipelines; i++) {
crtc = &kms->crtcs[kms->n_crtcs];
master = mdev->pipelines[i];
crtc->master = master;
crtc->slave = NULL;
if (crtc->slave)
sprintf(str, "pipe-%d", crtc->slave->id);
else
sprintf(str, "None");
DRM_INFO("crtc%d: master(pipe-%d) slave(%s) output: %s.\n",
kms->n_crtcs, master->id, str,
master->of_output_dev ?
master->of_output_dev->full_name : "None");
kms->n_crtcs++;
}
return 0;
}
static struct drm_plane *
get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc)
{
struct komeda_plane *kplane;
struct drm_plane *plane;
drm_for_each_plane(plane, &kms->base) {
if (plane->type != DRM_PLANE_TYPE_PRIMARY)
continue;
kplane = to_kplane(plane);
/* only master can be primary */
if (kplane->layer->base.pipeline == crtc->master)
return plane;
}
return NULL;
}
static int komeda_crtc_add(struct komeda_kms_dev *kms,
struct komeda_crtc *kcrtc)
{
struct drm_crtc *crtc = &kcrtc->base;
int err;
err = drm_crtc_init_with_planes(&kms->base, crtc,
get_crtc_primary(kms, kcrtc), NULL,
&komeda_crtc_funcs, NULL);
if (err)
return err;
drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs);
drm_crtc_vblank_reset(crtc);
crtc->port = kcrtc->master->of_output_port;
return 0;
}
int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev)
{
int i, err;
for (i = 0; i < kms->n_crtcs; i++) {
err = komeda_crtc_add(kms, &kms->crtcs[i]);
if (err)
return err;
}
return 0;
}

186
drivers/gpu/drm/arm/display/komeda/komeda_dev.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include "komeda_dev.h"
static int komeda_parse_pipe_dt(struct komeda_dev *mdev, struct device_node *np)
{
struct komeda_pipeline *pipe;
struct clk *clk;
u32 pipe_id;
int ret = 0;
ret = of_property_read_u32(np, "reg", &pipe_id);
if (ret != 0 || pipe_id >= mdev->n_pipelines)
return -EINVAL;
pipe = mdev->pipelines[pipe_id];
clk = of_clk_get_by_name(np, "aclk");
if (IS_ERR(clk)) {
DRM_ERROR("get aclk for pipeline %d failed!\n", pipe_id);
return PTR_ERR(clk);
}
pipe->aclk = clk;
clk = of_clk_get_by_name(np, "pxclk");
if (IS_ERR(clk)) {
DRM_ERROR("get pxclk for pipeline %d failed!\n", pipe_id);
return PTR_ERR(clk);
}
pipe->pxlclk = clk;
/* enum ports */
pipe->of_output_dev =
of_graph_get_remote_node(np, KOMEDA_OF_PORT_OUTPUT, 0);
pipe->of_output_port =
of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT);
pipe->of_node = np;
return 0;
}
static int komeda_parse_dt(struct device *dev, struct komeda_dev *mdev)
{
struct device_node *child, *np = dev->of_node;
struct clk *clk;
int ret;
clk = devm_clk_get(dev, "mclk");
if (IS_ERR(clk))
return PTR_ERR(clk);
mdev->mclk = clk;
for_each_available_child_of_node(np, child) {
if (of_node_cmp(child->name, "pipeline") == 0) {
ret = komeda_parse_pipe_dt(mdev, child);
if (ret) {
DRM_ERROR("parse pipeline dt error!\n");
of_node_put(child);
break;
}
}
}
return ret;
}
struct komeda_dev *komeda_dev_create(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
const struct komeda_product_data *product;
struct komeda_dev *mdev;
struct resource *io_res;
int err = 0;
product = of_device_get_match_data(dev);
if (!product)
return ERR_PTR(-ENODEV);
io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!io_res) {
DRM_ERROR("No registers defined.\n");
return ERR_PTR(-ENODEV);
}
mdev = devm_kzalloc(dev, sizeof(*mdev), GFP_KERNEL);
if (!mdev)
return ERR_PTR(-ENOMEM);
mdev->dev = dev;
mdev->reg_base = devm_ioremap_resource(dev, io_res);
if (IS_ERR(mdev->reg_base)) {
DRM_ERROR("Map register space failed.\n");
err = PTR_ERR(mdev->reg_base);
mdev->reg_base = NULL;
goto err_cleanup;
}
mdev->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(mdev->pclk)) {
DRM_ERROR("Get APB clk failed.\n");
err = PTR_ERR(mdev->pclk);
mdev->pclk = NULL;
goto err_cleanup;
}
/* Enable APB clock to access the registers */
clk_prepare_enable(mdev->pclk);
mdev->funcs = product->identify(mdev->reg_base, &mdev->chip);
if (!komeda_product_match(mdev, product->product_id)) {
DRM_ERROR("DT configured %x mismatch with real HW %x.\n",
product->product_id,
MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id));
err = -ENODEV;
goto err_cleanup;
}
DRM_INFO("Found ARM Mali-D%x version r%dp%d\n",
MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id),
MALIDP_CORE_ID_MAJOR(mdev->chip.core_id),
MALIDP_CORE_ID_MINOR(mdev->chip.core_id));
mdev->funcs->init_format_table(mdev);
err = mdev->funcs->enum_resources(mdev);
if (err) {
DRM_ERROR("enumerate display resource failed.\n");
goto err_cleanup;
}
err = komeda_parse_dt(dev, mdev);
if (err) {
DRM_ERROR("parse device tree failed.\n");
goto err_cleanup;
}
return mdev;
err_cleanup:
komeda_dev_destroy(mdev);
return ERR_PTR(err);
}
void komeda_dev_destroy(struct komeda_dev *mdev)
{
struct device *dev = mdev->dev;
struct komeda_dev_funcs *funcs = mdev->funcs;
int i;
for (i = 0; i < mdev->n_pipelines; i++) {
komeda_pipeline_destroy(mdev, mdev->pipelines[i]);
mdev->pipelines[i] = NULL;
}
mdev->n_pipelines = 0;
if (funcs && funcs->cleanup)
funcs->cleanup(mdev);
if (mdev->reg_base) {
devm_iounmap(dev, mdev->reg_base);
mdev->reg_base = NULL;
}
if (mdev->mclk) {
devm_clk_put(dev, mdev->mclk);
mdev->mclk = NULL;
}
if (mdev->pclk) {
clk_disable_unprepare(mdev->pclk);
devm_clk_put(dev, mdev->pclk);
mdev->pclk = NULL;
}
devm_kfree(dev, mdev);
}

110
drivers/gpu/drm/arm/display/komeda/komeda_dev.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _KOMEDA_DEV_H_
#define _KOMEDA_DEV_H_
#include <linux/device.h>
#include <linux/clk.h>
#include "komeda_pipeline.h"
#include "malidp_product.h"
#include "komeda_format_caps.h"
/* malidp device id */
enum {
MALI_D71 = 0,
};
/* pipeline DT ports */
enum {
KOMEDA_OF_PORT_OUTPUT = 0,
KOMEDA_OF_PORT_COPROC = 1,
};
struct komeda_chip_info {
u32 arch_id;
u32 core_id;
u32 core_info;
u32 bus_width;
};
struct komeda_product_data {
u32 product_id;
struct komeda_dev_funcs *(*identify)(u32 __iomem *reg,
struct komeda_chip_info *info);
};
struct komeda_dev;
/**
* struct komeda_dev_funcs
*
* Supplied by chip level and returned by the chip entry function xxx_identify,
*/
struct komeda_dev_funcs {
/**
* @init_format_table:
*
* initialize &komeda_dev->format_table, this function should be called
* before the &enum_resource
*/
void (*init_format_table)(struct komeda_dev *mdev);
/**
* @enum_resources:
*
* for CHIP to report or add pipeline and component resources to CORE
*/
int (*enum_resources)(struct komeda_dev *mdev);
/** @cleanup: call to chip to cleanup komeda_dev->chip data */
void (*cleanup)(struct komeda_dev *mdev);
};
/**
* struct komeda_dev
*
* Pipeline and component are used to describe how to handle the pixel data.
* komeda_device is for describing the whole view of the device, and the
* control-abilites of device.
*/
struct komeda_dev {
struct device *dev;
u32 __iomem *reg_base;
struct komeda_chip_info chip;
/** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
struct komeda_format_caps_table fmt_tbl;
/** @pclk: APB clock for register access */
struct clk *pclk;
/** @mck: HW main engine clk */
struct clk *mclk;
int n_pipelines;
struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
/** @funcs: chip funcs to access to HW */
struct komeda_dev_funcs *funcs;
/**
* @chip_data:
*
* chip data will be added by &komeda_dev_funcs.enum_resources() and
* destroyed by &komeda_dev_funcs.cleanup()
*/
void *chip_data;
};
static inline bool
komeda_product_match(struct komeda_dev *mdev, u32 target)
{
return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
}
struct komeda_dev_funcs *
d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
struct komeda_dev *komeda_dev_create(struct device *dev);
void komeda_dev_destroy(struct komeda_dev *mdev);
#endif /*_KOMEDA_DEV_H_*/

144
drivers/gpu/drm/arm/display/komeda/komeda_drv.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/component.h>
#include <drm/drm_of.h>
#include "komeda_dev.h"
#include "komeda_kms.h"
struct komeda_drv {
struct komeda_dev *mdev;
struct komeda_kms_dev *kms;
};
static void komeda_unbind(struct device *dev)
{
struct komeda_drv *mdrv = dev_get_drvdata(dev);
if (!mdrv)
return;
komeda_kms_detach(mdrv->kms);
komeda_dev_destroy(mdrv->mdev);
dev_set_drvdata(dev, NULL);
devm_kfree(dev, mdrv);
}
static int komeda_bind(struct device *dev)
{
struct komeda_drv *mdrv;
int err;
mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);
if (!mdrv)
return -ENOMEM;
mdrv->mdev = komeda_dev_create(dev);
if (IS_ERR(mdrv->mdev)) {
err = PTR_ERR(mdrv->mdev);
goto free_mdrv;
}
mdrv->kms = komeda_kms_attach(mdrv->mdev);
if (IS_ERR(mdrv->kms)) {
err = PTR_ERR(mdrv->kms);
goto destroy_mdev;
}
dev_set_drvdata(dev, mdrv);
return 0;
destroy_mdev:
komeda_dev_destroy(mdrv->mdev);
free_mdrv:
devm_kfree(dev, mdrv);
return err;
}
static const struct component_master_ops komeda_master_ops = {
.bind = komeda_bind,
.unbind = komeda_unbind,
};
static int compare_of(struct device *dev, void *data)
{
return dev->of_node == data;
}
static void komeda_add_slave(struct device *master,
struct component_match **match,
struct device_node *np, int port)
{
struct device_node *remote;
remote = of_graph_get_remote_node(np, port, 0);
if (remote) {
drm_of_component_match_add(master, match, compare_of, remote);
of_node_put(remote);
}
}
static int komeda_platform_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct component_match *match = NULL;
struct device_node *child;
if (!dev->of_node)
return -ENODEV;
for_each_available_child_of_node(dev->of_node, child) {
if (of_node_cmp(child->name, "pipeline") != 0)
continue;
/* add connector */
komeda_add_slave(dev, &match, child, KOMEDA_OF_PORT_OUTPUT);
}
return component_master_add_with_match(dev, &komeda_master_ops, match);
}
static int komeda_platform_remove(struct platform_device *pdev)
{
component_master_del(&pdev->dev, &komeda_master_ops);
return 0;
}
static const struct komeda_product_data komeda_products[] = {
[MALI_D71] = {
.product_id = MALIDP_D71_PRODUCT_ID,
.identify = d71_identify,
},
};
const struct of_device_id komeda_of_match[] = {
{ .compatible = "arm,mali-d71", .data = &komeda_products[MALI_D71], },
{},
};
MODULE_DEVICE_TABLE(of, komeda_of_match);
static struct platform_driver komeda_platform_driver = {
.probe = komeda_platform_probe,
.remove = komeda_platform_remove,
.driver = {
.name = "komeda",
.of_match_table = komeda_of_match,
.pm = NULL,
},
};
module_platform_driver(komeda_platform_driver);
MODULE_AUTHOR("James.Qian.Wang <james.qian.wang@arm.com>");
MODULE_DESCRIPTION("Komeda KMS driver");
MODULE_LICENSE("GPL v2");

75
drivers/gpu/drm/arm/display/komeda/komeda_format_caps.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <linux/slab.h>
#include "komeda_format_caps.h"
#include "malidp_utils.h"
const struct komeda_format_caps *
komeda_get_format_caps(struct komeda_format_caps_table *table,
u32 fourcc, u64 modifier)
{
const struct komeda_format_caps *caps;
u64 afbc_features = modifier & ~(AFBC_FORMAT_MOD_BLOCK_SIZE_MASK);
u32 afbc_layout = modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_MASK;
int id;
for (id = 0; id < table->n_formats; id++) {
caps = &table->format_caps[id];
if (fourcc != caps->fourcc)
continue;
if ((modifier == 0ULL) && (caps->supported_afbc_layouts == 0))
return caps;
if (has_bits(afbc_features, caps->supported_afbc_features) &&
has_bit(afbc_layout, caps->supported_afbc_layouts))
return caps;
}
return NULL;
}
u32 *komeda_get_layer_fourcc_list(struct komeda_format_caps_table *table,
u32 layer_type, u32 *n_fmts)
{
const struct komeda_format_caps *cap;
u32 *fmts;
int i, j, n = 0;
fmts = kcalloc(table->n_formats, sizeof(u32), GFP_KERNEL);
if (!fmts)
return NULL;
for (i = 0; i < table->n_formats; i++) {
cap = &table->format_caps[i];
if (!(layer_type & cap->supported_layer_types) ||
(cap->fourcc == 0))
continue;
/* one fourcc may has two caps items in table (afbc/none-afbc),
* so check the existing list to avoid adding a duplicated one.
*/
for (j = n - 1; j >= 0; j--)
if (fmts[j] == cap->fourcc)
break;
if (j < 0)
fmts[n++] = cap->fourcc;
}
if (n_fmts)
*n_fmts = n;
return fmts;
}
void komeda_put_fourcc_list(u32 *fourcc_list)
{
kfree(fourcc_list);
}

89
drivers/gpu/drm/arm/display/komeda/komeda_format_caps.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _KOMEDA_FORMAT_CAPS_H_
#define _KOMEDA_FORMAT_CAPS_H_
#include <linux/types.h>
#include <uapi/drm/drm_fourcc.h>
#include <drm/drm_fourcc.h>
#define AFBC(x) DRM_FORMAT_MOD_ARM_AFBC(x)
/* afbc layerout */
#define AFBC_16x16(x) AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | (x))
#define AFBC_32x8(x) AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | (x))
/* afbc features */
#define _YTR AFBC_FORMAT_MOD_YTR
#define _SPLIT AFBC_FORMAT_MOD_SPLIT
#define _SPARSE AFBC_FORMAT_MOD_SPARSE
#define _CBR AFBC_FORMAT_MOD_CBR
#define _TILED AFBC_FORMAT_MOD_TILED
#define _SC AFBC_FORMAT_MOD_SC
/* layer_type */
#define KOMEDA_FMT_RICH_LAYER BIT(0)
#define KOMEDA_FMT_SIMPLE_LAYER BIT(1)
#define KOMEDA_FMT_WB_LAYER BIT(2)
#define AFBC_TH_LAYOUT_ALIGNMENT 8
#define AFBC_HEADER_SIZE 16
#define AFBC_SUPERBLK_ALIGNMENT 128
#define AFBC_SUPERBLK_PIXELS 256
#define AFBC_BODY_START_ALIGNMENT 1024
#define AFBC_TH_BODY_START_ALIGNMENT 4096
/**
* struct komeda_format_caps
*
* komeda_format_caps is for describing ARM display specific features and
* limitations for a specific format, and format_caps will be linked into
* &komeda_framebuffer like a extension of &drm_format_info.
*
* NOTE: one fourcc may has two different format_caps items for fourcc and
* fourcc+modifier
*
* @hw_id: hw format id, hw specific value.
* @fourcc: drm fourcc format.
* @tile_size: format tiled size, used by ARM format X0L0/X0L2
* @supported_layer_types: indicate which layer supports this format
* @supported_rots: allowed rotations for this format
* @supported_afbc_layouts: supported afbc layerout
* @supported_afbc_features: supported afbc features
*/
struct komeda_format_caps {
u32 hw_id;
u32 fourcc;
u32 tile_size;
u32 supported_layer_types;
u32 supported_rots;
u32 supported_afbc_layouts;
u64 supported_afbc_features;
};
/**
* struct komeda_format_caps_table - format_caps mananger
*
* @n_formats: the size of format_caps list.
* @format_caps: format_caps list.
*/
struct komeda_format_caps_table {
u32 n_formats;
const struct komeda_format_caps *format_caps;
};
const struct komeda_format_caps *
komeda_get_format_caps(struct komeda_format_caps_table *table,
u32 fourcc, u64 modifier);
u32 *komeda_get_layer_fourcc_list(struct komeda_format_caps_table *table,
u32 layer_type, u32 *n_fmts);
void komeda_put_fourcc_list(u32 *fourcc_list);
#endif

165
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <drm/drm_gem.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include "komeda_framebuffer.h"
#include "komeda_dev.h"
static void komeda_fb_destroy(struct drm_framebuffer *fb)
{
struct komeda_fb *kfb = to_kfb(fb);
u32 i;
for (i = 0; i < fb->format->num_planes; i++)
drm_gem_object_put_unlocked(fb->obj[i]);
drm_framebuffer_cleanup(fb);
kfree(kfb);
}
static int komeda_fb_create_handle(struct drm_framebuffer *fb,
struct drm_file *file, u32 *handle)
{
return drm_gem_handle_create(file, fb->obj[0], handle);
}
static const struct drm_framebuffer_funcs komeda_fb_funcs = {
.destroy = komeda_fb_destroy,
.create_handle = komeda_fb_create_handle,
};
static int
komeda_fb_none_afbc_size_check(struct komeda_dev *mdev, struct komeda_fb *kfb,
struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd)
{
struct drm_framebuffer *fb = &kfb->base;
struct drm_gem_object *obj;
u32 min_size = 0;
u32 i;
for (i = 0; i < fb->format->num_planes; i++) {
obj = drm_gem_object_lookup(file, mode_cmd->handles[i]);
if (!obj) {
DRM_DEBUG_KMS("Failed to lookup GEM object\n");
fb->obj[i] = NULL;
return -ENOENT;
}
kfb->aligned_w = fb->width / (i ? fb->format->hsub : 1);
kfb->aligned_h = fb->height / (i ? fb->format->vsub : 1);
if (fb->pitches[i] % mdev->chip.bus_width) {
DRM_DEBUG_KMS("Pitch[%d]: 0x%x doesn't align to 0x%x\n",
i, fb->pitches[i], mdev->chip.bus_width);
drm_gem_object_put_unlocked(obj);
fb->obj[i] = NULL;
return -EINVAL;
}
min_size = ((kfb->aligned_h / kfb->format_caps->tile_size - 1)
* fb->pitches[i])
+ (kfb->aligned_w * fb->format->cpp[i]
* kfb->format_caps->tile_size)
+ fb->offsets[i];
if (obj->size < min_size) {
DRM_DEBUG_KMS("Fail to check none afbc fb size.\n");
drm_gem_object_put_unlocked(obj);
fb->obj[i] = NULL;
return -EINVAL;
}
fb->obj[i] = obj;
}
if (fb->format->num_planes == 3) {
if (fb->pitches[1] != fb->pitches[2]) {
DRM_DEBUG_KMS("The pitch[1] and [2] are not same\n");
return -EINVAL;
}
}
return 0;
}
struct drm_framebuffer *
komeda_fb_create(struct drm_device *dev, struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd)
{
struct komeda_dev *mdev = dev->dev_private;
struct komeda_fb *kfb;
int ret = 0, i;
kfb = kzalloc(sizeof(*kfb), GFP_KERNEL);
if (!kfb)
return ERR_PTR(-ENOMEM);
kfb->format_caps = komeda_get_format_caps(&mdev->fmt_tbl,
mode_cmd->pixel_format,
mode_cmd->modifier[0]);
if (!kfb->format_caps) {
DRM_DEBUG_KMS("FMT %x is not supported.\n",
mode_cmd->pixel_format);
kfree(kfb);
return ERR_PTR(-EINVAL);
}
drm_helper_mode_fill_fb_struct(dev, &kfb->base, mode_cmd);
ret = komeda_fb_none_afbc_size_check(mdev, kfb, file, mode_cmd);
if (ret < 0)
goto err_cleanup;
ret = drm_framebuffer_init(dev, &kfb->base, &komeda_fb_funcs);
if (ret < 0) {
DRM_DEBUG_KMS("failed to initialize fb\n");
goto err_cleanup;
}
return &kfb->base;
err_cleanup:
for (i = 0; i < kfb->base.format->num_planes; i++)
drm_gem_object_put_unlocked(kfb->base.obj[i]);
kfree(kfb);
return ERR_PTR(ret);
}
dma_addr_t
komeda_fb_get_pixel_addr(struct komeda_fb *kfb, int x, int y, int plane)
{
struct drm_framebuffer *fb = &kfb->base;
const struct drm_gem_cma_object *obj;
u32 plane_x, plane_y, cpp, pitch, offset;
if (plane >= fb->format->num_planes) {
DRM_DEBUG_KMS("Out of max plane num.\n");
return -EINVAL;
}
obj = drm_fb_cma_get_gem_obj(fb, plane);
offset = fb->offsets[plane];
if (!fb->modifier) {
plane_x = x / (plane ? fb->format->hsub : 1);
plane_y = y / (plane ? fb->format->vsub : 1);
cpp = fb->format->cpp[plane];
pitch = fb->pitches[plane];
offset += plane_x * cpp * kfb->format_caps->tile_size +
(plane_y * pitch) / kfb->format_caps->tile_size;
}
return obj->paddr + offset;
}

34
drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h Normal file
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@@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _KOMEDA_FRAMEBUFFER_H_
#define _KOMEDA_FRAMEBUFFER_H_
#include <drm/drm_framebuffer.h>
#include "komeda_format_caps.h"
/** struct komeda_fb - entend drm_framebuffer with komeda attribute */
struct komeda_fb {
/** @base: &drm_framebuffer */
struct drm_framebuffer base;
/* @format_caps: &komeda_format_caps */
const struct komeda_format_caps *format_caps;
/** @aligned_w: aligned frame buffer width */
u32 aligned_w;
/** @aligned_h: aligned frame buffer height */
u32 aligned_h;
};
#define to_kfb(dfb) container_of(dfb, struct komeda_fb, base)
struct drm_framebuffer *
komeda_fb_create(struct drm_device *dev, struct drm_file *file,
const struct drm_mode_fb_cmd2 *mode_cmd);
dma_addr_t
komeda_fb_get_pixel_addr(struct komeda_fb *kfb, int x, int y, int plane);
bool komeda_fb_is_layer_supported(struct komeda_fb *kfb, u32 layer_type);
#endif

167
drivers/gpu/drm/arm/display/komeda/komeda_kms.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <linux/component.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_helper.h>
#include <linux/interrupt.h>
#include "komeda_dev.h"
#include "komeda_kms.h"
#include "komeda_framebuffer.h"
DEFINE_DRM_GEM_CMA_FOPS(komeda_cma_fops);
static int komeda_gem_cma_dumb_create(struct drm_file *file,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
u32 alignment = 16; /* TODO get alignment from dev */
args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8),
alignment);
return drm_gem_cma_dumb_create_internal(file, dev, args);
}
static struct drm_driver komeda_kms_driver = {
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
DRIVER_PRIME,
.lastclose = drm_fb_helper_lastclose,
.gem_free_object_unlocked = drm_gem_cma_free_object,
.gem_vm_ops = &drm_gem_cma_vm_ops,
.dumb_create = komeda_gem_cma_dumb_create,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = drm_gem_prime_export,
.gem_prime_import = drm_gem_prime_import,
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
.gem_prime_vmap = drm_gem_cma_prime_vmap,
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
.gem_prime_mmap = drm_gem_cma_prime_mmap,
.fops = &komeda_cma_fops,
.name = "komeda",
.desc = "Arm Komeda Display Processor driver",
.date = "20181101",
.major = 0,
.minor = 1,
};
static void komeda_kms_commit_tail(struct drm_atomic_state *old_state)
{
struct drm_device *dev = old_state->dev;
drm_atomic_helper_commit_modeset_disables(dev, old_state);
drm_atomic_helper_commit_planes(dev, old_state, 0);
drm_atomic_helper_commit_modeset_enables(dev, old_state);
drm_atomic_helper_wait_for_flip_done(dev, old_state);
drm_atomic_helper_commit_hw_done(old_state);
drm_atomic_helper_cleanup_planes(dev, old_state);
}
static const struct drm_mode_config_helper_funcs komeda_mode_config_helpers = {
.atomic_commit_tail = komeda_kms_commit_tail,
};
static const struct drm_mode_config_funcs komeda_mode_config_funcs = {
.fb_create = komeda_fb_create,
.atomic_check = drm_atomic_helper_check,
.atomic_commit = drm_atomic_helper_commit,
};
static void komeda_kms_mode_config_init(struct komeda_kms_dev *kms,
struct komeda_dev *mdev)
{
struct drm_mode_config *config = &kms->base.mode_config;
drm_mode_config_init(&kms->base);
komeda_kms_setup_crtcs(kms, mdev);
/* Get value from dev */
config->min_width = 0;
config->min_height = 0;
config->max_width = 4096;
config->max_height = 4096;
config->allow_fb_modifiers = false;
config->funcs = &komeda_mode_config_funcs;
config->helper_private = &komeda_mode_config_helpers;
}
struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev)
{
struct komeda_kms_dev *kms = kzalloc(sizeof(*kms), GFP_KERNEL);
struct drm_device *drm;
int err;
if (!kms)
return ERR_PTR(-ENOMEM);
drm = &kms->base;
err = drm_dev_init(drm, &komeda_kms_driver, mdev->dev);
if (err)
goto free_kms;
drm->dev_private = mdev;
komeda_kms_mode_config_init(kms, mdev);
err = komeda_kms_add_private_objs(kms, mdev);
if (err)
goto cleanup_mode_config;
err = komeda_kms_add_planes(kms, mdev);
if (err)
goto cleanup_mode_config;
err = drm_vblank_init(drm, kms->n_crtcs);
if (err)
goto cleanup_mode_config;
err = komeda_kms_add_crtcs(kms, mdev);
if (err)
goto cleanup_mode_config;
err = component_bind_all(mdev->dev, kms);
if (err)
goto cleanup_mode_config;
drm_mode_config_reset(drm);
err = drm_dev_register(drm, 0);
if (err)
goto cleanup_mode_config;
return kms;
cleanup_mode_config:
drm_mode_config_cleanup(drm);
free_kms:
kfree(kms);
return ERR_PTR(err);
}
void komeda_kms_detach(struct komeda_kms_dev *kms)
{
struct drm_device *drm = &kms->base;
struct komeda_dev *mdev = drm->dev_private;
drm_dev_unregister(drm);
component_unbind_all(mdev->dev, drm);
komeda_kms_cleanup_private_objs(mdev);
drm_mode_config_cleanup(drm);
drm->dev_private = NULL;
drm_dev_put(drm);
}

113
drivers/gpu/drm/arm/display/komeda/komeda_kms.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _KOMEDA_KMS_H_
#define _KOMEDA_KMS_H_
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_writeback.h>
/** struct komeda_plane - komeda instance of drm_plane */
struct komeda_plane {
/** @base: &drm_plane */
struct drm_plane base;
/**
* @layer:
*
* represents available layer input pipelines for this plane.
*
* NOTE:
* the layer is not for a specific Layer, but indicate a group of
* Layers with same capabilities.
*/
struct komeda_layer *layer;
};
/**
* struct komeda_plane_state
*
* The plane_state can be split into two data flow (left/right) and handled
* by two layers &komeda_plane.layer and &komeda_plane.layer.right
*/
struct komeda_plane_state {
/** @base: &drm_plane_state */
struct drm_plane_state base;
/* private properties */
};
/**
* struct komeda_wb_connector
*/
struct komeda_wb_connector {
/** @base: &drm_writeback_connector */
struct drm_writeback_connector base;
/** @wb_layer: represents associated writeback pipeline of komeda */
struct komeda_layer *wb_layer;
};
/**
* struct komeda_crtc
*/
struct komeda_crtc {
/** @base: &drm_crtc */
struct drm_crtc base;
/** @master: only master has display output */
struct komeda_pipeline *master;
/**
* @slave: optional
*
* Doesn't have its own display output, the handled data flow will
* merge into the master.
*/
struct komeda_pipeline *slave;
};
/** struct komeda_crtc_state */
struct komeda_crtc_state {
/** @base: &drm_crtc_state */
struct drm_crtc_state base;
/* private properties */
/* computed state which are used by validate/check */
u32 affected_pipes;
u32 active_pipes;
};
/** struct komeda_kms_dev - for gather KMS related things */
struct komeda_kms_dev {
/** @base: &drm_device */
struct drm_device base;
/** @n_crtcs: valid numbers of crtcs in &komeda_kms_dev.crtcs */
int n_crtcs;
/** @crtcs: crtcs list */
struct komeda_crtc crtcs[KOMEDA_MAX_PIPELINES];
};
#define to_kplane(p) container_of(p, struct komeda_plane, base)
#define to_kplane_st(p) container_of(p, struct komeda_plane_state, base)
#define to_kconn(p) container_of(p, struct komeda_wb_connector, base)
#define to_kcrtc(p) container_of(p, struct komeda_crtc, base)
#define to_kcrtc_st(p) container_of(p, struct komeda_crtc_state, base)
#define to_kdev(p) container_of(p, struct komeda_kms_dev, base)
int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev);
int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev);
int komeda_kms_add_planes(struct komeda_kms_dev *kms, struct komeda_dev *mdev);
int komeda_kms_add_private_objs(struct komeda_kms_dev *kms,
struct komeda_dev *mdev);
void komeda_kms_cleanup_private_objs(struct komeda_dev *mdev);
struct komeda_kms_dev *komeda_kms_attach(struct komeda_dev *mdev);
void komeda_kms_detach(struct komeda_kms_dev *kms);
#endif /*_KOMEDA_KMS_H_*/

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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include "komeda_dev.h"
#include "komeda_pipeline.h"
/** komeda_pipeline_add - Add a pipeline to &komeda_dev */
struct komeda_pipeline *
komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
struct komeda_pipeline_funcs *funcs)
{
struct komeda_pipeline *pipe;
if (mdev->n_pipelines + 1 > KOMEDA_MAX_PIPELINES) {
DRM_ERROR("Exceed max support %d pipelines.\n",
KOMEDA_MAX_PIPELINES);
return NULL;
}
if (size < sizeof(*pipe)) {
DRM_ERROR("Request pipeline size too small.\n");
return NULL;
}
pipe = devm_kzalloc(mdev->dev, size, GFP_KERNEL);
if (!pipe)
return NULL;
pipe->mdev = mdev;
pipe->id = mdev->n_pipelines;
pipe->funcs = funcs;
mdev->pipelines[mdev->n_pipelines] = pipe;
mdev->n_pipelines++;
return pipe;
}
void komeda_pipeline_destroy(struct komeda_dev *mdev,
struct komeda_pipeline *pipe)
{
struct komeda_component *c;
int i;
dp_for_each_set_bit(i, pipe->avail_comps) {
c = komeda_pipeline_get_component(pipe, i);
komeda_component_destroy(mdev, c);
}
clk_put(pipe->pxlclk);
clk_put(pipe->aclk);
of_node_put(pipe->of_output_dev);
of_node_put(pipe->of_output_port);
of_node_put(pipe->of_node);
devm_kfree(mdev->dev, pipe);
}
struct komeda_component **
komeda_pipeline_get_component_pos(struct komeda_pipeline *pipe, int id)
{
struct komeda_dev *mdev = pipe->mdev;
struct komeda_pipeline *temp = NULL;
struct komeda_component **pos = NULL;
switch (id) {
case KOMEDA_COMPONENT_LAYER0:
case KOMEDA_COMPONENT_LAYER1:
case KOMEDA_COMPONENT_LAYER2:
case KOMEDA_COMPONENT_LAYER3:
pos = to_cpos(pipe->layers[id - KOMEDA_COMPONENT_LAYER0]);
break;
case KOMEDA_COMPONENT_WB_LAYER:
pos = to_cpos(pipe->wb_layer);
break;
case KOMEDA_COMPONENT_COMPIZ0:
case KOMEDA_COMPONENT_COMPIZ1:
temp = mdev->pipelines[id - KOMEDA_COMPONENT_COMPIZ0];
if (!temp) {
DRM_ERROR("compiz-%d doesn't exist.\n", id);
return NULL;
}
pos = to_cpos(temp->compiz);
break;
case KOMEDA_COMPONENT_SCALER0:
case KOMEDA_COMPONENT_SCALER1:
pos = to_cpos(pipe->scalers[id - KOMEDA_COMPONENT_SCALER0]);
break;
case KOMEDA_COMPONENT_IPS0:
case KOMEDA_COMPONENT_IPS1:
temp = mdev->pipelines[id - KOMEDA_COMPONENT_IPS0];
if (!temp) {
DRM_ERROR("ips-%d doesn't exist.\n", id);
return NULL;
}
pos = to_cpos(temp->improc);
break;
case KOMEDA_COMPONENT_TIMING_CTRLR:
pos = to_cpos(pipe->ctrlr);
break;
default:
pos = NULL;
DRM_ERROR("Unknown pipeline resource ID: %d.\n", id);
break;
}
return pos;
}
struct komeda_component *
komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id)
{
struct komeda_component **pos = NULL;
struct komeda_component *c = NULL;
pos = komeda_pipeline_get_component_pos(pipe, id);
if (pos)
c = *pos;
return c;
}
/** komeda_component_add - Add a component to &komeda_pipeline */
struct komeda_component *
komeda_component_add(struct komeda_pipeline *pipe,
size_t comp_sz, u32 id, u32 hw_id,
struct komeda_component_funcs *funcs,
u8 max_active_inputs, u32 supported_inputs,
u8 max_active_outputs, u32 __iomem *reg,
const char *name_fmt, ...)
{
struct komeda_component **pos;
struct komeda_component *c;
int idx, *num = NULL;
if (max_active_inputs > KOMEDA_COMPONENT_N_INPUTS) {
WARN(1, "please large KOMEDA_COMPONENT_N_INPUTS to %d.\n",
max_active_inputs);
return NULL;
}
pos = komeda_pipeline_get_component_pos(pipe, id);
if (!pos || (*pos))
return NULL;
if (has_bit(id, KOMEDA_PIPELINE_LAYERS)) {
idx = id - KOMEDA_COMPONENT_LAYER0;
num = &pipe->n_layers;
if (idx != pipe->n_layers) {
DRM_ERROR("please add Layer by id sequence.\n");
return NULL;
}
} else if (has_bit(id, KOMEDA_PIPELINE_SCALERS)) {
idx = id - KOMEDA_COMPONENT_SCALER0;
num = &pipe->n_scalers;
if (idx != pipe->n_scalers) {
DRM_ERROR("please add Scaler by id sequence.\n");
return NULL;
}
}
c = devm_kzalloc(pipe->mdev->dev, comp_sz, GFP_KERNEL);
if (!c)
return NULL;
c->id = id;
c->hw_id = hw_id;
c->reg = reg;
c->pipeline = pipe;
c->max_active_inputs = max_active_inputs;
c->max_active_outputs = max_active_outputs;
c->supported_inputs = supported_inputs;
c->funcs = funcs;
if (name_fmt) {
va_list args;
va_start(args, name_fmt);
vsnprintf(c->name, sizeof(c->name), name_fmt, args);
va_end(args);
}
if (num)
*num = *num + 1;
pipe->avail_comps |= BIT(c->id);
*pos = c;
return c;
}
void komeda_component_destroy(struct komeda_dev *mdev,
struct komeda_component *c)
{
devm_kfree(mdev->dev, c);
}

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#ifndef _KOMEDA_PIPELINE_H_
#define _KOMEDA_PIPELINE_H_
#include <linux/types.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include "malidp_utils.h"
#define KOMEDA_MAX_PIPELINES 2
#define KOMEDA_PIPELINE_MAX_LAYERS 4
#define KOMEDA_PIPELINE_MAX_SCALERS 2
#define KOMEDA_COMPONENT_N_INPUTS 5
/* pipeline component IDs */
enum {
KOMEDA_COMPONENT_LAYER0 = 0,
KOMEDA_COMPONENT_LAYER1 = 1,
KOMEDA_COMPONENT_LAYER2 = 2,
KOMEDA_COMPONENT_LAYER3 = 3,
KOMEDA_COMPONENT_WB_LAYER = 7, /* write back layer */
KOMEDA_COMPONENT_SCALER0 = 8,
KOMEDA_COMPONENT_SCALER1 = 9,
KOMEDA_COMPONENT_SPLITTER = 12,
KOMEDA_COMPONENT_MERGER = 14,
KOMEDA_COMPONENT_COMPIZ0 = 16, /* compositor */
KOMEDA_COMPONENT_COMPIZ1 = 17,
KOMEDA_COMPONENT_IPS0 = 20, /* post image processor */
KOMEDA_COMPONENT_IPS1 = 21,
KOMEDA_COMPONENT_TIMING_CTRLR = 22, /* timing controller */
};
#define KOMEDA_PIPELINE_LAYERS (BIT(KOMEDA_COMPONENT_LAYER0) |\
BIT(KOMEDA_COMPONENT_LAYER1) |\
BIT(KOMEDA_COMPONENT_LAYER2) |\
BIT(KOMEDA_COMPONENT_LAYER3))
#define KOMEDA_PIPELINE_SCALERS (BIT(KOMEDA_COMPONENT_SCALER0) |\
BIT(KOMEDA_COMPONENT_SCALER1))
#define KOMEDA_PIPELINE_COMPIZS (BIT(KOMEDA_COMPONENT_COMPIZ0) |\
BIT(KOMEDA_COMPONENT_COMPIZ1))
#define KOMEDA_PIPELINE_IMPROCS (BIT(KOMEDA_COMPONENT_IPS0) |\
BIT(KOMEDA_COMPONENT_IPS1))
struct komeda_component;
struct komeda_component_state;
/** komeda_component_funcs - component control functions */
struct komeda_component_funcs {
/** @validate: optional,
* component may has special requirements or limitations, this function
* supply HW the ability to do the further HW specific check.
*/
int (*validate)(struct komeda_component *c,
struct komeda_component_state *state);
/** @update: update is a active update */
void (*update)(struct komeda_component *c,
struct komeda_component_state *state);
/** @disable: disable component */
void (*disable)(struct komeda_component *c);
/** @dump_register: Optional, dump registers to seq_file */
void (*dump_register)(struct komeda_component *c, struct seq_file *seq);
};
/**
* struct komeda_component
*
* struct komeda_component describe the data flow capabilities for how to link a
* component into the display pipeline.
* all specified components are subclass of this structure.
*/
struct komeda_component {
/** @obj: treat component as private obj */
struct drm_private_obj obj;
/** @pipeline: the komeda pipeline this component belongs to */
struct komeda_pipeline *pipeline;
/** @name: component name */
char name[32];
/**
* @reg:
* component register base,
* which is initialized by chip and used by chip only
*/
u32 __iomem *reg;
/** @id: component id */
u32 id;
/** @hw_ic: component hw id,
* which is initialized by chip and used by chip only
*/
u32 hw_id;
/**
* @max_active_inputs:
* @max_active_outpus:
*
* maximum number of inputs/outputs that can be active in the same time
* Note:
* the number isn't the bit number of @supported_inputs or
* @supported_outputs, but may be less than it, since component may not
* support enabling all @supported_inputs/outputs at the same time.
*/
u8 max_active_inputs;
u8 max_active_outputs;
/**
* @supported_inputs:
* @supported_outputs:
*
* bitmask of BIT(component->id) for the supported inputs/outputs
* describes the possibilities of how a component is linked into a
* pipeline.
*/
u32 supported_inputs;
u32 supported_outputs;
/**
* @funcs: chip functions to access HW
*/
struct komeda_component_funcs *funcs;
};
/**
* struct komeda_component_output
*
* a component has multiple outputs, if want to know where the data
* comes from, only know the component is not enough, we still need to know
* its output port
*/
struct komeda_component_output {
/** @component: indicate which component the data comes from */
struct komeda_component *component;
/** @output_port:
* the output port of the &komeda_component_output.component
*/
u8 output_port;
};
/**
* struct komeda_component_state
*
* component_state is the data flow configuration of the component, and it's
* the superclass of all specific component_state like @komeda_layer_state,
* @komeda_scaler_state
*/
struct komeda_component_state {
/** @obj: tracking component_state by drm_atomic_state */
struct drm_private_state obj;
struct komeda_component *component;
/**
* @binding_user:
* currently bound user, the user can be crtc/plane/wb_conn, which is
* valid decided by @component and @inputs
*
* - Layer: its user always is plane.
* - compiz/improc/timing_ctrlr: the user is crtc.
* - wb_layer: wb_conn;
* - scaler: plane when input is layer, wb_conn if input is compiz.
*/
union {
struct drm_crtc *crtc;
struct drm_plane *plane;
struct drm_connector *wb_conn;
void *binding_user;
};
/**
* @active_inputs:
*
* active_inputs is bitmask of @inputs index
*
* - active_inputs = changed_active_inputs + unchanged_active_inputs
* - affected_inputs = old->active_inputs + new->active_inputs;
* - disabling_inputs = affected_inputs ^ active_inputs;
* - changed_inputs = disabling_inputs + changed_active_inputs;
*
* NOTE:
* changed_inputs doesn't include all active_input but only
* @changed_active_inputs, and this bitmask can be used in chip
* level for dirty update.
*/
u16 active_inputs;
u16 changed_active_inputs;
u16 affected_inputs;
/**
* @inputs:
*
* the specific inputs[i] only valid on BIT(i) has been set in
* @active_inputs, if not the inputs[i] is undefined.
*/
struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS];
};
static inline u16 component_disabling_inputs(struct komeda_component_state *st)
{
return st->affected_inputs ^ st->active_inputs;
}
static inline u16 component_changed_inputs(struct komeda_component_state *st)
{
return component_disabling_inputs(st) | st->changed_active_inputs;
}
#define to_comp(__c) (((__c) == NULL) ? NULL : &((__c)->base))
#define to_cpos(__c) ((struct komeda_component **)&(__c))
/* these structures are going to be filled in in uture patches */
struct komeda_layer {
struct komeda_component base;
/* layer specific features and caps */
int layer_type; /* RICH, SIMPLE or WB */
};
struct komeda_layer_state {
struct komeda_component_state base;
/* layer specific configuration state */
};
struct komeda_compiz {
struct komeda_component base;
/* compiz specific features and caps */
};
struct komeda_compiz_state {
struct komeda_component_state base;
/* compiz specific configuration state */
};
struct komeda_scaler {
struct komeda_component base;
/* scaler features and caps */
};
struct komeda_scaler_state {
struct komeda_component_state base;
};
struct komeda_improc {
struct komeda_component base;
};
struct komeda_improc_state {
struct komeda_component_state base;
};
/* display timing controller */
struct komeda_timing_ctrlr {
struct komeda_component base;
};
struct komeda_timing_ctrlr_state {
struct komeda_component_state base;
};
/** struct komeda_pipeline_funcs */
struct komeda_pipeline_funcs {
/* dump_register: Optional, dump registers to seq_file */
void (*dump_register)(struct komeda_pipeline *pipe,
struct seq_file *sf);
};
/**
* struct komeda_pipeline
*
* Represent a complete display pipeline and hold all functional components.
*/
struct komeda_pipeline {
/** @obj: link pipeline as private obj of drm_atomic_state */
struct drm_private_obj obj;
/** @mdev: the parent komeda_dev */
struct komeda_dev *mdev;
/** @pxlclk: pixel clock */
struct clk *pxlclk;
/** @aclk: AXI clock */
struct clk *aclk;
/** @id: pipeline id */
int id;
/** @avail_comps: available components mask of pipeline */
u32 avail_comps;
int n_layers;
struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS];
int n_scalers;
struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS];
struct komeda_compiz *compiz;
struct komeda_layer *wb_layer;
struct komeda_improc *improc;
struct komeda_timing_ctrlr *ctrlr;
struct komeda_pipeline_funcs *funcs; /* private pipeline functions */
/** @of_node: pipeline dt node */
struct device_node *of_node;
/** @of_output_port: pipeline output port */
struct device_node *of_output_port;
/** @of_output_dev: output connector device node */
struct device_node *of_output_dev;
};
/**
* struct komeda_pipeline_state
*
* NOTE:
* Unlike the pipeline, pipeline_state doesn’t gather any component_state
* into it. It because all component will be managed by drm_atomic_state.
*/
struct komeda_pipeline_state {
/** @obj: tracking pipeline_state by drm_atomic_state */
struct drm_private_state obj;
struct komeda_pipeline *pipe;
/** @crtc: currently bound crtc */
struct drm_crtc *crtc;
/**
* @active_comps:
*
* bitmask - BIT(component->id) of active components
*/
u32 active_comps;
};
#define to_layer(c) container_of(c, struct komeda_layer, base)
#define to_compiz(c) container_of(c, struct komeda_compiz, base)
#define to_scaler(c) container_of(c, struct komeda_scaler, base)
#define to_improc(c) container_of(c, struct komeda_improc, base)
#define to_ctrlr(c) container_of(c, struct komeda_timing_ctrlr, base)
#define to_layer_st(c) container_of(c, struct komeda_layer_state, base)
#define to_compiz_st(c) container_of(c, struct komeda_compiz_state, base)
#define to_scaler_st(c) container_of(c, struct komeda_scaler_state, base)
#define to_improc_st(c) container_of(c, struct komeda_improc_state, base)
#define to_ctrlr_st(c) container_of(c, struct komeda_timing_ctrlr_state, base)
#define priv_to_comp_st(o) container_of(o, struct komeda_component_state, obj)
#define priv_to_pipe_st(o) container_of(o, struct komeda_pipeline_state, obj)
/* pipeline APIs */
struct komeda_pipeline *
komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
struct komeda_pipeline_funcs *funcs);
void komeda_pipeline_destroy(struct komeda_dev *mdev,
struct komeda_pipeline *pipe);
struct komeda_component *
komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id);
/* component APIs */
struct komeda_component *
komeda_component_add(struct komeda_pipeline *pipe,
size_t comp_sz, u32 id, u32 hw_id,
struct komeda_component_funcs *funcs,
u8 max_active_inputs, u32 supported_inputs,
u8 max_active_outputs, u32 __iomem *reg,
const char *name_fmt, ...);
void komeda_component_destroy(struct komeda_dev *mdev,
struct komeda_component *c);
#endif /* _KOMEDA_PIPELINE_H_*/

109
drivers/gpu/drm/arm/display/komeda/komeda_plane.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_plane_helper.h>
#include "komeda_dev.h"
#include "komeda_kms.h"
static const struct drm_plane_helper_funcs komeda_plane_helper_funcs = {
};
static void komeda_plane_destroy(struct drm_plane *plane)
{
drm_plane_cleanup(plane);
kfree(to_kplane(plane));
}
static const struct drm_plane_funcs komeda_plane_funcs = {
};
/* for komeda, which is pipeline can be share between crtcs */
static u32 get_possible_crtcs(struct komeda_kms_dev *kms,
struct komeda_pipeline *pipe)
{
struct komeda_crtc *crtc;
u32 possible_crtcs = 0;
int i;
for (i = 0; i < kms->n_crtcs; i++) {
crtc = &kms->crtcs[i];
if ((pipe == crtc->master) || (pipe == crtc->slave))
possible_crtcs |= BIT(i);
}
return possible_crtcs;
}
/* use Layer0 as primary */
static u32 get_plane_type(struct komeda_kms_dev *kms,
struct komeda_component *c)
{
bool is_primary = (c->id == KOMEDA_COMPONENT_LAYER0);
return is_primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
}
static int komeda_plane_add(struct komeda_kms_dev *kms,
struct komeda_layer *layer)
{
struct komeda_dev *mdev = kms->base.dev_private;
struct komeda_component *c = &layer->base;
struct komeda_plane *kplane;
struct drm_plane *plane;
u32 *formats, n_formats = 0;
int err;
kplane = kzalloc(sizeof(*kplane), GFP_KERNEL);
if (!kplane)
return -ENOMEM;
plane = &kplane->base;
kplane->layer = layer;
formats = komeda_get_layer_fourcc_list(&mdev->fmt_tbl,
layer->layer_type, &n_formats);
err = drm_universal_plane_init(&kms->base, plane,
get_possible_crtcs(kms, c->pipeline),
&komeda_plane_funcs,
formats, n_formats, NULL,
get_plane_type(kms, c),
"%s", c->name);
komeda_put_fourcc_list(formats);
if (err)
goto cleanup;
drm_plane_helper_add(plane, &komeda_plane_helper_funcs);
return 0;
cleanup:
komeda_plane_destroy(plane);
return err;
}
int komeda_kms_add_planes(struct komeda_kms_dev *kms, struct komeda_dev *mdev)
{
struct komeda_pipeline *pipe;
int i, j, err;
for (i = 0; i < mdev->n_pipelines; i++) {
pipe = mdev->pipelines[i];
for (j = 0; j < pipe->n_layers; j++) {
err = komeda_plane_add(kms, pipe->layers[j]);
if (err)
return err;
}
}
return 0;
}

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drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
* Author: James.Qian.Wang <james.qian.wang@arm.com>
*
*/
#include "komeda_dev.h"
#include "komeda_kms.h"
static struct drm_private_state *
komeda_pipeline_atomic_duplicate_state(struct drm_private_obj *obj)
{
struct komeda_pipeline_state *st;
st = kmemdup(obj->state, sizeof(*st), GFP_KERNEL);
if (!st)
return NULL;
st->active_comps = 0;
__drm_atomic_helper_private_obj_duplicate_state(obj, &st->obj);
return &st->obj;
}
static void
komeda_pipeline_atomic_destroy_state(struct drm_private_obj *obj,
struct drm_private_state *state)
{
kfree(priv_to_pipe_st(state));
}
static const struct drm_private_state_funcs komeda_pipeline_obj_funcs = {
.atomic_duplicate_state = komeda_pipeline_atomic_duplicate_state,
.atomic_destroy_state = komeda_pipeline_atomic_destroy_state,
};
static int komeda_pipeline_obj_add(struct komeda_kms_dev *kms,
struct komeda_pipeline *pipe)
{
struct komeda_pipeline_state *st;
st = kzalloc(sizeof(*st), GFP_KERNEL);
if (!st)
return -ENOMEM;
st->pipe = pipe;
drm_atomic_private_obj_init(&kms->base, &pipe->obj, &st->obj,
&komeda_pipeline_obj_funcs);
return 0;
}
int komeda_kms_add_private_objs(struct komeda_kms_dev *kms,
struct komeda_dev *mdev)
{
struct komeda_pipeline *pipe;
int i, err;
for (i = 0; i < mdev->n_pipelines; i++) {
pipe = mdev->pipelines[i];
err = komeda_pipeline_obj_add(kms, pipe);
if (err)
return err;
/* Add component */
}
return 0;
}
void komeda_kms_cleanup_private_objs(struct komeda_dev *mdev)
{
struct komeda_pipeline *pipe;
struct komeda_component *c;
int i, id;
for (i = 0; i < mdev->n_pipelines; i++) {
pipe = mdev->pipelines[i];
dp_for_each_set_bit(id, pipe->avail_comps) {
c = komeda_pipeline_get_component(pipe, id);
drm_atomic_private_obj_fini(&c->obj);
}
drm_atomic_private_obj_fini(&pipe->obj);
}
}