Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 4.14 for MIPS; below a summary of
the non-merge commits:
CM:
- Rename mips_cm_base to mips_gcr_base
- Specify register size when generating accessors
- Use BIT/GENMASK for register fields, order & drop shifts
- Add cluster & block args to mips_cm_lock_other()
CPC:
- Use common CPS accessor generation macros
- Use BIT/GENMASK for register fields, order & drop shifts
- Introduce register modify (set/clear/change) accessors
- Use change_*, set_* & clear_* where appropriate
- Add CM/CPC 3.5 register definitions
- Use GlobalNumber macros rather than magic numbers
- Have asm/mips-cps.h include CM & CPC headers
- Cluster support for topology functions
- Detect CPUs in secondary clusters
CPS:
- Read GIC_VL_IDENT directly, not via irqchip driver
DMA:
- Consolidate coherent and non-coherent dma_alloc code
- Don't use dma_cache_sync to implement fd_cacheflush
FPU emulation / FP assist code:
- Another series of 14 commits fixing corner cases such as NaN
propgagation and other special input values.
- Zero bits 32-63 of the result for a CLASS.D instruction.
- Enhanced statics via debugfs
- Do not use bools for arithmetic. GCC 7.1 moans about this.
- Correct user fault_addr type
Generic MIPS:
- Enhancement of stack backtraces
- Cleanup from non-existing options
- Handle non word sized instructions when examining frame
- Fix detection and decoding of ADDIUSP instruction
- Fix decoding of SWSP16 instruction
- Refactor handling of stack pointer in get_frame_info
- Remove unreachable code from force_fcr31_sig()
- Convert to using %pOF instead of full_name
- Remove the R6000 support.
- Move FP code from *_switch.S to *_fpu.S
- Remove unused ST_OFF from r2300_switch.S
- Allow platform to specify multiple its.S files
- Add #includes to various files to ensure code builds reliable and
without warning..
- Remove __invalidate_kernel_vmap_range
- Remove plat_timer_setup
- Declare various variables & functions static
- Abstract CPU core & VP(E) ID access through accessor functions
- Store core & VP IDs in GlobalNumber-style variable
- Unify checks for sibling CPUs
- Add CPU cluster number accessors
- Prevent direct use of generic_defconfig
- Make CONFIG_MIPS_MT_SMP default y
- Add __ioread64_copy
- Remove unnecessary inclusions of linux/irqchip/mips-gic.h
GIC:
- Introduce asm/mips-gic.h with accessor functions
- Use new GIC accessor functions in mips-gic-timer
- Remove counter access functions from irq-mips-gic.c
- Remove gic_read_local_vp_id() from irq-mips-gic.c
- Simplify shared interrupt pending/mask reads in irq-mips-gic.c
- Simplify gic_local_irq_domain_map() in irq-mips-gic.c
- Drop gic_(re)set_mask() functions in irq-mips-gic.c
- Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
- Convert remaining shared reg access, local int mask access and
remaining local reg access to new accessors
- Move GIC_LOCAL_INT_* to asm/mips-gic.h
- Remove GIC_CPU_INT* macros from irq-mips-gic.c
- Move various definitions to the driver
- Remove gic_get_usm_range()
- Remove __gic_irq_dispatch() forward declaration
- Remove gic_init()
- Use mips_gic_present() in place of gic_present and remove
gic_present
- Move gic_get_c0_*_int() to asm/mips-gic.h
- Remove linux/irqchip/mips-gic.h
- Inline __gic_init()
- Inline gic_basic_init()
- Make pcpu_masks a per-cpu variable
- Use pcpu_masks to avoid reading GIC_SH_MASK*
- Clean up mti, reserved-cpu-vectors handling
- Use cpumask_first_and() in gic_set_affinity()
- Let the core set struct irq_common_data affinity
microMIPS:
- Fix microMIPS stack unwinding on big endian systems
MIPS-GIC:
- SYNC after enabling GIC region
NUMA:
- Remove the unused parent_node() macro
R6:
- Constify r2_decoder_tables
- Add accessor & bit definitions for GlobalNumber
SMP:
- Constify smp ops
- Allow boot_secondary SMP op to return errors
VDSO:
- Drop gic_get_usm_range() usage
- Avoid use of linux/irqchip/mips-gic.h
Platform changes:
Alchemy:
- Add devboard machine type to cpuinfo
- update cpu feature overrides
- Threaded carddetect irqs for devboards
AR7:
- allow NULL clock for clk_get_rate
BCM63xx:
- Fix ENETDMA_6345_MAXBURST_REG offset
- Allow NULL clock for clk_get_rate
CI20:
- Enable GPIO and RTC drivers in defconfig
- Add ethernet and fixed-regulator nodes to DTS
Generic platform:
- Move Boston and NI 169445 FIT image source to their own files
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Allow filtering enabled boards by requirements
- Don't explicitly disable CONFIG_USB_SUPPORT
- Bump default NR_CPUS to 16
JZ4700:
- Probe the jz4740-rtc driver from devicetree
Lantiq:
- Drop check of boot select from the spi-falcon driver.
- Drop check of boot select from the lantiq-flash MTD driver.
- Access boot cause register in the watchdog driver through regmap
- Add device tree binding documentation for the watchdog driver
- Add docs for the RCU DT bindings.
- Convert the fpi bus driver to a platform_driver
- Remove ltq_reset_cause() and ltq_boot_select(
- Switch to a proper reset driver
- Switch to a new drivers/soc GPHY driver
- Add an USB PHY driver for the Lantiq SoCs using the RCU module
- Use of_platform_default_populate instead of __dt_register_buses
- Enable MFD_SYSCON to be able to use it for the RCU MFD
- Replace ltq_boot_select() with dummy implementation.
Loongson 2F:
- Allow NULL clock for clk_get_rate
Malta:
- Use new GIC accessor functions
NI 169445:
- Add support for NI 169445 board.
- Only include in 32r2el kernels
Octeon:
- Add support for watchdog of 78XX SOCs.
- Add support for watchdog of CN68XX SOCs.
- Expose support for mips32r1, mips32r2 and mips64r1
- Enable more drivers in config file
- Add support for accessing the boot vector.
- Remove old boot vector code from watchdog driver
- Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
- Make CSR functions node aware.
- Allow access to CIU3 IRQ domains.
- Misc cleanups in the watchdog driver
Omega2+:
- New board, add support and defconfig
Pistachio:
- Enable Root FS on NFS in defconfig
Ralink:
- Add Mediatek MT7628A SoC
- Allow NULL clock for clk_get_rate
- Explicitly request exclusive reset control in the pci-mt7620 PCI driver.
SEAD3:
- Only include in 32 bit kernels by default
VoCore:
- Add VoCore as a vendor t0 dt-bindings
- Add defconfig file"
* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
MIPS: Refactor handling of stack pointer in get_frame_info
MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
MIPS: microMIPS: Fix decoding of swsp16 instruction
MIPS: microMIPS: Fix decoding of addiusp instruction
MIPS: microMIPS: Fix detection of addiusp instruction
MIPS: Handle non word sized instructions when examining frame
MIPS: ralink: allow NULL clock for clk_get_rate
MIPS: Loongson 2F: allow NULL clock for clk_get_rate
MIPS: BCM63XX: allow NULL clock for clk_get_rate
MIPS: AR7: allow NULL clock for clk_get_rate
MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
mips: Save all registers when saving the frame
MIPS: Add DWARF unwinding to assembly
MIPS: Make SAVE_SOME more standard
MIPS: Fix issues in backtraces
MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
MIPS: Ci20: Enable RTC driver
watchdog: octeon-wdt: Add support for 78XX SOCs.
watchdog: octeon-wdt: Add support for cn68XX SOCs.
watchdog: octeon-wdt: File cleaning.
...
This commit is contained in:
Linus Torvalds
@@ -1,297 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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*/
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#ifndef __LINUX_IRQCHIP_MIPS_GIC_H
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#define __LINUX_IRQCHIP_MIPS_GIC_H
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#include <linux/clocksource.h>
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#include <linux/ioport.h>
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#define GIC_MAX_INTRS 256
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/* Constants */
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#define GIC_POL_POS 1
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#define GIC_POL_NEG 0
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#define GIC_TRIG_EDGE 1
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#define GIC_TRIG_LEVEL 0
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#define GIC_TRIG_DUAL_ENABLE 1
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#define GIC_TRIG_DUAL_DISABLE 0
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#define MSK(n) ((1 << (n)) - 1)
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/* Accessors */
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#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
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/* GIC Address Space */
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#define SHARED_SECTION_OFS 0x0000
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#define SHARED_SECTION_SIZE 0x8000
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#define VPE_LOCAL_SECTION_OFS 0x8000
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#define VPE_LOCAL_SECTION_SIZE 0x4000
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#define VPE_OTHER_SECTION_OFS 0xc000
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#define VPE_OTHER_SECTION_SIZE 0x4000
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#define USM_VISIBLE_SECTION_OFS 0x10000
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#define USM_VISIBLE_SECTION_SIZE 0x10000
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/* Register Map for Shared Section */
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#define GIC_SH_CONFIG_OFS 0x0000
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/* Shared Global Counter */
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#define GIC_SH_COUNTER_31_00_OFS 0x0010
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/* 64-bit counter register for CM3 */
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#define GIC_SH_COUNTER_OFS GIC_SH_COUNTER_31_00_OFS
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#define GIC_SH_COUNTER_63_32_OFS 0x0014
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#define GIC_SH_REVISIONID_OFS 0x0020
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/* Convert an interrupt number to a byte offset/bit for multi-word registers */
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#define GIC_INTR_OFS(intr) ({ \
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unsigned bits = mips_cm_is64 ? 64 : 32; \
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unsigned reg_idx = (intr) / bits; \
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unsigned reg_width = bits / 8; \
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\
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reg_idx * reg_width; \
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})
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#define GIC_INTR_BIT(intr) ((intr) % (mips_cm_is64 ? 64 : 32))
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/* Polarity : Reset Value is always 0 */
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#define GIC_SH_SET_POLARITY_OFS 0x0100
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/* Triggering : Reset Value is always 0 */
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#define GIC_SH_SET_TRIGGER_OFS 0x0180
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/* Dual edge triggering : Reset Value is always 0 */
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#define GIC_SH_SET_DUAL_OFS 0x0200
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/* Set/Clear corresponding bit in Edge Detect Register */
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#define GIC_SH_WEDGE_OFS 0x0280
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/* Mask manipulation */
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#define GIC_SH_RMASK_OFS 0x0300
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#define GIC_SH_SMASK_OFS 0x0380
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/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
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#define GIC_SH_MASK_OFS 0x0400
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/* Pending Global Interrupts (RO) */
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#define GIC_SH_PEND_OFS 0x0480
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/* Maps Interrupt X to a Pin */
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#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
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#define GIC_SH_MAP_TO_PIN(intr) (4 * (intr))
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/* Maps Interrupt X to a VPE */
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#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
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#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
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((32 * (intr)) + (((vpe) / 32) * 4))
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#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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#define GIC_VPE_PEND_OFS 0x0004
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#define GIC_VPE_MASK_OFS 0x0008
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#define GIC_VPE_RMASK_OFS 0x000c
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#define GIC_VPE_SMASK_OFS 0x0010
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#define GIC_VPE_WD_MAP_OFS 0x0040
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#define GIC_VPE_COMPARE_MAP_OFS 0x0044
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#define GIC_VPE_TIMER_MAP_OFS 0x0048
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#define GIC_VPE_FDC_MAP_OFS 0x004c
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#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
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#define GIC_VPE_SWINT0_MAP_OFS 0x0054
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#define GIC_VPE_SWINT1_MAP_OFS 0x0058
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#define GIC_VPE_OTHER_ADDR_OFS 0x0080
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#define GIC_VP_IDENT_OFS 0x0088
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#define GIC_VPE_WD_CONFIG0_OFS 0x0090
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#define GIC_VPE_WD_COUNT0_OFS 0x0094
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#define GIC_VPE_WD_INITIAL0_OFS 0x0098
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#define GIC_VPE_COMPARE_LO_OFS 0x00a0
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/* 64-bit Compare register on CM3 */
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#define GIC_VPE_COMPARE_OFS GIC_VPE_COMPARE_LO_OFS
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#define GIC_VPE_COMPARE_HI_OFS 0x00a4
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#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
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#define GIC_VPE_EIC_SS(intr) (4 * (intr))
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#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800
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#define GIC_VPE_EIC_VEC(intr) (4 * (intr))
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#define GIC_VPE_TENABLE_NMI_OFS 0x1000
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#define GIC_VPE_TENABLE_YQ_OFS 0x1004
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#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
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#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
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/* User Mode Visible Section Register Map */
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#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
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#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
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/* Masks */
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#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
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#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
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#define GIC_SH_CONFIG_COUNTBITS_SHF 24
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#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
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#define GIC_SH_CONFIG_NUMINTRS_SHF 16
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#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
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#define GIC_SH_CONFIG_NUMVPES_SHF 0
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#define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
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#define GIC_SH_WEDGE_SET(intr) ((intr) | (0x1 << 31))
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#define GIC_SH_WEDGE_CLR(intr) ((intr) & ~(0x1 << 31))
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#define GIC_MAP_TO_PIN_SHF 31
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#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
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#define GIC_MAP_TO_NMI_SHF 30
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#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
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#define GIC_MAP_TO_YQ_SHF 29
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#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
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#define GIC_MAP_SHF 0
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#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
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/* GIC_VPE_CTL Masks */
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#define GIC_VPE_CTL_FDC_RTBL_SHF 4
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#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
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#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
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#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
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#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
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#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
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#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
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#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
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#define GIC_VPE_CTL_EIC_MODE_SHF 0
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#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
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/* GIC_VPE_PEND Masks */
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#define GIC_VPE_PEND_WD_SHF 0
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#define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
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#define GIC_VPE_PEND_CMP_SHF 1
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#define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
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#define GIC_VPE_PEND_TIMER_SHF 2
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#define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
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#define GIC_VPE_PEND_PERFCOUNT_SHF 3
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#define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
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#define GIC_VPE_PEND_SWINT0_SHF 4
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#define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
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#define GIC_VPE_PEND_SWINT1_SHF 5
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#define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
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#define GIC_VPE_PEND_FDC_SHF 6
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#define GIC_VPE_PEND_FDC_MSK (MSK(1) << GIC_VPE_PEND_FDC_SHF)
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/* GIC_VPE_RMASK Masks */
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#define GIC_VPE_RMASK_WD_SHF 0
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#define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
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#define GIC_VPE_RMASK_CMP_SHF 1
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#define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
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#define GIC_VPE_RMASK_TIMER_SHF 2
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#define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
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#define GIC_VPE_RMASK_PERFCNT_SHF 3
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#define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
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#define GIC_VPE_RMASK_SWINT0_SHF 4
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#define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
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#define GIC_VPE_RMASK_SWINT1_SHF 5
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#define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
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#define GIC_VPE_RMASK_FDC_SHF 6
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#define GIC_VPE_RMASK_FDC_MSK (MSK(1) << GIC_VPE_RMASK_FDC_SHF)
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/* GIC_VPE_SMASK Masks */
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#define GIC_VPE_SMASK_WD_SHF 0
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#define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
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#define GIC_VPE_SMASK_CMP_SHF 1
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#define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
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#define GIC_VPE_SMASK_TIMER_SHF 2
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#define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
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#define GIC_VPE_SMASK_PERFCNT_SHF 3
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#define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
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#define GIC_VPE_SMASK_SWINT0_SHF 4
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#define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
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#define GIC_VPE_SMASK_SWINT1_SHF 5
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#define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
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#define GIC_VPE_SMASK_FDC_SHF 6
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#define GIC_VPE_SMASK_FDC_MSK (MSK(1) << GIC_VPE_SMASK_FDC_SHF)
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/* GIC_VP_IDENT fields */
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#define GIC_VP_IDENT_VCNUM_SHF 0
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#define GIC_VP_IDENT_VCNUM_MSK (MSK(6) << GIC_VP_IDENT_VCNUM_SHF)
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/* GIC nomenclature for Core Interrupt Pins. */
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#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
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#define GIC_CPU_INT1 1 /* . */
|
||||
#define GIC_CPU_INT2 2 /* . */
|
||||
#define GIC_CPU_INT3 3 /* . */
|
||||
#define GIC_CPU_INT4 4 /* . */
|
||||
#define GIC_CPU_INT5 5 /* Core Interrupt 7 */
|
||||
|
||||
/* Add 2 to convert GIC CPU pin to core interrupt */
|
||||
#define GIC_CPU_PIN_OFFSET 2
|
||||
|
||||
/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
|
||||
#define GIC_CPU_TO_VEC_OFFSET 2
|
||||
|
||||
/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
|
||||
#define GIC_PIN_TO_VEC_OFFSET 1
|
||||
|
||||
/* Local GIC interrupts. */
|
||||
#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */
|
||||
#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */
|
||||
#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */
|
||||
#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */
|
||||
#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */
|
||||
#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */
|
||||
#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */
|
||||
#define GIC_NUM_LOCAL_INTRS 7
|
||||
|
||||
/* Convert between local/shared IRQ number and GIC HW IRQ number. */
|
||||
#define GIC_LOCAL_HWIRQ_BASE 0
|
||||
#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
|
||||
#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
|
||||
#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
|
||||
#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
|
||||
#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
|
||||
|
||||
#ifdef CONFIG_MIPS_GIC
|
||||
|
||||
extern unsigned int gic_present;
|
||||
|
||||
extern void gic_init(unsigned long gic_base_addr,
|
||||
unsigned long gic_addrspace_size, unsigned int cpu_vec,
|
||||
unsigned int irqbase);
|
||||
extern u64 gic_read_count(void);
|
||||
extern unsigned int gic_get_count_width(void);
|
||||
extern u64 gic_read_compare(void);
|
||||
extern void gic_write_compare(u64 cnt);
|
||||
extern void gic_write_cpu_compare(u64 cnt, int cpu);
|
||||
extern void gic_start_count(void);
|
||||
extern void gic_stop_count(void);
|
||||
extern int gic_get_c0_compare_int(void);
|
||||
extern int gic_get_c0_perfcount_int(void);
|
||||
extern int gic_get_c0_fdc_int(void);
|
||||
extern int gic_get_usm_range(struct resource *gic_usm_res);
|
||||
|
||||
#else /* CONFIG_MIPS_GIC */
|
||||
|
||||
#define gic_present 0
|
||||
|
||||
static inline int gic_get_usm_range(struct resource *gic_usm_res)
|
||||
{
|
||||
/* Shouldn't be called. */
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MIPS_GIC */
|
||||
|
||||
/**
|
||||
* gic_read_local_vp_id() - read the local VPs VCNUM
|
||||
*
|
||||
* Read the VCNUM of the local VP from the GIC_VP_IDENT register and
|
||||
* return it to the caller. This ID should be used to refer to the VP
|
||||
* via the GICs VP-other region, or when calculating an offset to a
|
||||
* bit representing the VP in interrupt masks.
|
||||
*
|
||||
* Return: The VCNUM value for the local VP.
|
||||
*/
|
||||
extern unsigned gic_read_local_vp_id(void);
|
||||
|
||||
#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
|
||||
Reference in New Issue
Block a user