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[IA64] spelling fixes: arch/ia64/

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Spelling and apostrophe fixes in arch/ia64/.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Simon Arlott
2007-05-11 14:55:43 -07:00
committed by Tony Luck
parent 0a3fd051c7
commit 72fdbdce3d
30 changed files with 75 additions and 75 deletions
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16
arch/ia64/sn/pci/tioce_provider.c
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@@ -256,9 +256,9 @@ pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
* @ct_addr: the coretalk address to map
* @len: number of bytes to map
*
* Given the addressing type, set up various paramaters that define the
* Given the addressing type, set up various parameters that define the
* ATE pool to use. Search for a contiguous block of entries to cover the
* length, and if enough resources exist, fill in the ATE's and construct a
* length, and if enough resources exist, fill in the ATEs and construct a
* tioce_dmamap struct to track the mapping.
*/
static u64
@@ -581,8 +581,8 @@ tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count,
*/
if (!mapaddr && !barrier && dma_mask >= 0xffffffffffUL) {
/*
* We have two options for 40-bit mappings: 16GB "super" ATE's
* and 64MB "regular" ATE's. We'll try both if needed for a
* We have two options for 40-bit mappings: 16GB "super" ATEs
* and 64MB "regular" ATEs. We'll try both if needed for a
* given mapping but which one we try first depends on the
* size. For requests >64MB, prefer to use a super page with
* regular as the fallback. Otherwise, try in the reverse order.
@@ -687,8 +687,8 @@ tioce_error_intr_handler(int irq, void *arg)
}
/**
* tioce_reserve_m32 - reserve M32 ate's for the indicated address range
* @tioce_kernel: TIOCE context to reserve ate's for
* tioce_reserve_m32 - reserve M32 ATEs for the indicated address range
* @tioce_kernel: TIOCE context to reserve ATEs for
* @base: starting bus address to reserve
* @limit: last bus address to reserve
*
@@ -763,7 +763,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
/*
* Set PMU pagesize to the largest size available, and zero out
* the ate's.
* the ATEs.
*/
tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
@@ -784,7 +784,7 @@ tioce_kern_init(struct tioce_common *tioce_common)
}
/*
* Reserve ATE's corresponding to reserved address ranges. These
* Reserve ATEs corresponding to reserved address ranges. These
* include:
*
* Memory space covered by each PPB mem base/limit register