Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Fix out-of-sync IVs in self-test for IPsec AEAD algorithms Algorithms: - Use formally verified implementation of x86/curve25519 Drivers: - Enhance hwrng support in caam - Use crypto_engine for skcipher/aead/rsa/hash in caam - Add Xilinx AES driver - Add uacce driver - Register zip engine to uacce in hisilicon - Add support for OCTEON TX CPT engine in marvell" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (162 commits) crypto: af_alg - bool type cosmetics crypto: arm[64]/poly1305 - add artifact to .gitignore files crypto: caam - limit single JD RNG output to maximum of 16 bytes crypto: caam - enable prediction resistance in HRWNG bus: fsl-mc: add api to retrieve mc version crypto: caam - invalidate entropy register during RNG initialization crypto: caam - check if RNG job failed crypto: caam - simplify RNG implementation crypto: caam - drop global context pointer and init_done crypto: caam - use struct hwrng's .init for initialization crypto: caam - allocate RNG instantiation descriptor with GFP_DMA crypto: ccree - remove duplicated include from cc_aead.c crypto: chelsio - remove set but not used variable 'adap' crypto: marvell - enable OcteonTX cpt options for build crypto: marvell - add the Virtual Function driver for CPT crypto: marvell - add support for OCTEON TX CPT engine crypto: marvell - create common Kconfig and Makefile for Marvell crypto: arm/neon - memzero_explicit aes-cbc key crypto: bcm - Use scnprintf() for avoiding potential buffer overflow crypto: atmel-i2c - Fix wakeup fail ...
This commit is contained in:
Linus Torvalds
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Documentation/misc-devices/uacce.rst
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Documentation/misc-devices/uacce.rst
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.. SPDX-License-Identifier: GPL-2.0
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Introduction of Uacce
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---------------------
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Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
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provide Shared Virtual Addressing (SVA) between accelerators and processes.
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So accelerator can access any data structure of the main cpu.
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This differs from the data sharing between cpu and io device, which share
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only data content rather than address.
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Because of the unified address, hardware and user space of process can
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share the same virtual address in the communication.
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Uacce takes the hardware accelerator as a heterogeneous processor, while
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IOMMU share the same CPU page tables and as a result the same translation
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from va to pa.
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::
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__________________________ __________________________
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| | | |
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| User application (CPU) | | Hardware Accelerator |
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|__________________________| |__________________________|
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| |
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| va | va
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V V
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__________ __________
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| | | |
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| MMU | | IOMMU |
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|__________| |__________|
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| |
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| |
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V pa V pa
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_______________________________________
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| |
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| Memory |
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|_______________________________________|
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Architecture
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------------
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Uacce is the kernel module, taking charge of iommu and address sharing.
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The user drivers and libraries are called WarpDrive.
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The uacce device, built around the IOMMU SVA API, can access multiple
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address spaces, including the one without PASID.
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A virtual concept, queue, is used for the communication. It provides a
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FIFO-like interface. And it maintains a unified address space between the
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application and all involved hardware.
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::
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___________________ ________________
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| | user API | |
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| WarpDrive library | ------------> | user driver |
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|___________________| |________________|
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| queue fd |
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v |
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___________________ _________ |
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| | | | | mmap memory
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| Other framework | | uacce | | r/w interface
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| crypto/nic/others | |_________| |
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|___________________| |
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| | |
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| register | register |
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| | |
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| | |
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| _________________ __________ |
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| | | | | |
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------------- | Device Driver | | IOMMU | |
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|_________________| |__________| |
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| |
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| V
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| ___________________
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| | |
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-------------------------- | Device(Hardware) |
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|___________________|
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How does it work
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----------------
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Uacce uses mmap and IOMMU to play the trick.
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Uacce creates a chrdev for every device registered to it. New queue is
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created when user application open the chrdev. The file descriptor is used
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as the user handle of the queue.
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The accelerator device present itself as an Uacce object, which exports as
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a chrdev to the user space. The user application communicates with the
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hardware by ioctl (as control path) or share memory (as data path).
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The control path to the hardware is via file operation, while data path is
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via mmap space of the queue fd.
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The queue file address space:
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::
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/**
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* enum uacce_qfrt: qfrt type
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* @UACCE_QFRT_MMIO: device mmio region
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* @UACCE_QFRT_DUS: device user share region
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*/
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enum uacce_qfrt {
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UACCE_QFRT_MMIO = 0,
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UACCE_QFRT_DUS = 1,
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};
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All regions are optional and differ from device type to type.
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Each region can be mmapped only once, otherwise -EEXIST returns.
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The device mmio region is mapped to the hardware mmio space. It is generally
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used for doorbell or other notification to the hardware. It is not fast enough
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as data channel.
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The device user share region is used for share data buffer between user process
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and device.
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The Uacce register API
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----------------------
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The register API is defined in uacce.h.
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::
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struct uacce_interface {
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char name[UACCE_MAX_NAME_SIZE];
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unsigned int flags;
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const struct uacce_ops *ops;
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};
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According to the IOMMU capability, uacce_interface flags can be:
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::
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/**
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* UACCE Device flags:
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* UACCE_DEV_SVA: Shared Virtual Addresses
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* Support PASID
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* Support device page faults (PCI PRI or SMMU Stall)
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*/
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#define UACCE_DEV_SVA BIT(0)
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struct uacce_device *uacce_alloc(struct device *parent,
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struct uacce_interface *interface);
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int uacce_register(struct uacce_device *uacce);
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void uacce_remove(struct uacce_device *uacce);
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uacce_register results can be:
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a. If uacce module is not compiled, ERR_PTR(-ENODEV)
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b. Succeed with the desired flags
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c. Succeed with the negotiated flags, for example
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uacce_interface.flags = UACCE_DEV_SVA but uacce->flags = ~UACCE_DEV_SVA
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So user driver need check return value as well as the negotiated uacce->flags.
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The user driver
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---------------
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The queue file mmap space will need a user driver to wrap the communication
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protocol. Uacce provides some attributes in sysfs for the user driver to
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match the right accelerator accordingly.
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More details in Documentation/ABI/testing/sysfs-driver-uacce.
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