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arm64: gicv3: Allow GICv3 compilation with older binutils

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GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Olof Johansson <olof@lixom.net>
Tested-by: Olof Johansson <olof@lixom.net>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Catalin Marinas
2014-07-24 14:14:42 +01:00
parent ecb3c2bbf2
commit 72c5839515
4 changed files with 93 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/irqchip/irq-gic-v3.c
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@@ -108,39 +108,39 @@ static u64 gic_read_iar(void)
{
u64 irqstat;
asm volatile("mrs %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
return irqstat;
}
static void gic_write_pmr(u64 val)
{
asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));
}
static void gic_write_ctlr(u64 val)
{
asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));
isb();
}
static void gic_write_grpen1(u64 val)
{
asm volatile("msr " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));
isb();
}
static void gic_write_sgi1r(u64 val)
{
asm volatile("msr " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
}
static void gic_enable_sre(void)
{
u64 val;
asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
val |= ICC_SRE_EL1_SRE;
asm volatile("msr " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
isb();
/*
@@ -150,7 +150,7 @@ static void gic_enable_sre(void)
*
* Kindly inform the luser.
*/
asm volatile("mrs %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
if (!(val & ICC_SRE_EL1_SRE))
pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
}