pinctrl: st: Add Interrupt support
This patch add interrupt support to the pincontroller driver. ST Pincontroller GPIO bank can have one of the two possible types of interrupt-wirings. First type is via irqmux, single interrupt is used by multiple gpio banks. This reduces number of overall interrupts numbers required. All these banks belong to a single pincontroller. _________ | |----> [gpio-bank (n) ] | |----> [gpio-bank (n + 1)] [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |----> [gpio-bank (... )] |_________|----> [gpio-bank (n + 7)] Second type has a dedicated interrupt per gpio bank. [irqN]----> [gpio-bank (n)] Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Srinivas Kandagatla
committato da
Linus Walleij
Linus Walleij
parent
b28a960c42
commit
727b0f71a5
@@ -13,7 +13,12 @@
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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@@ -271,6 +276,7 @@ struct st_gpio_bank {
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struct pinctrl_gpio_range range;
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void __iomem *base;
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struct st_pio_control pc;
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struct irq_domain *domain;
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};
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struct st_pinctrl {
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@@ -284,6 +290,7 @@ struct st_pinctrl {
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int ngroups;
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struct regmap *regmap;
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const struct st_pctl_data *data;
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void __iomem *irqmux_base;
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};
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/* SOC specific data */
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@@ -1200,6 +1207,130 @@ static int st_pctl_parse_functions(struct device_node *np,
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return 0;
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}
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static int st_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
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int irq = -ENXIO;
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if (offset < chip->ngpio)
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irq = irq_find_mapping(bank->domain, offset);
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dev_info(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
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chip->label, offset + chip->base, irq);
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return irq;
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}
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static void st_gpio_irq_mask(struct irq_data *d)
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{
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struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
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}
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static void st_gpio_irq_unmask(struct irq_data *d)
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{
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struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
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}
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static unsigned int st_gpio_irq_startup(struct irq_data *d)
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{
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struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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if (gpio_lock_as_irq(&bank->gpio_chip, d->hwirq))
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dev_err(bank->gpio_chip.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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d->hwirq);
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st_gpio_irq_unmask(d);
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return 0;
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}
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static void st_gpio_irq_shutdown(struct irq_data *d)
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{
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struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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st_gpio_irq_mask(d);
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gpio_unlock_as_irq(&bank->gpio_chip, d->hwirq);
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}
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static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
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{
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struct st_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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int comp, pin = d->hwirq;
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u32 val;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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comp = 0;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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comp = 1;
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break;
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default:
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return -EINVAL;
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}
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val = readl(bank->base + REG_PIO_PCOMP);
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val &= ~BIT(pin);
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val |= (comp << pin);
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writel(val, bank->base + REG_PIO_PCOMP);
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return 0;
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}
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static void __gpio_irq_handler(struct st_gpio_bank *bank)
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{
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unsigned long port_in, port_mask, port_comp, active_irqs;
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int n;
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for (;;) {
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port_in = readl(bank->base + REG_PIO_PIN);
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port_comp = readl(bank->base + REG_PIO_PCOMP);
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port_mask = readl(bank->base + REG_PIO_PMASK);
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active_irqs = (port_in ^ port_comp) & port_mask;
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if (active_irqs == 0)
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break;
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for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
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generic_handle_irq(irq_find_mapping(bank->domain, n));
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}
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}
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}
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static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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/* interrupt dedicated per bank */
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struct irq_chip *chip = irq_get_chip(irq);
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struct st_gpio_bank *bank = irq_get_handler_data(irq);
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chained_irq_enter(chip, desc);
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__gpio_irq_handler(bank);
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chained_irq_exit(chip, desc);
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}
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static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct st_pinctrl *info = irq_get_handler_data(irq);
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unsigned long status;
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int n;
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chained_irq_enter(chip, desc);
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status = readl(info->irqmux_base);
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for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
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__gpio_irq_handler(&info->banks[n]);
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chained_irq_exit(chip, desc);
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}
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static struct gpio_chip st_gpio_template = {
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.request = st_gpio_request,
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.free = st_gpio_free,
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@@ -1210,6 +1341,34 @@ static struct gpio_chip st_gpio_template = {
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.ngpio = ST_GPIO_PINS_PER_BANK,
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.of_gpio_n_cells = 1,
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.of_xlate = st_gpio_xlate,
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.to_irq = st_gpio_to_irq,
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};
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static struct irq_chip st_gpio_irqchip = {
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.name = "GPIO",
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.irq_mask = st_gpio_irq_mask,
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.irq_unmask = st_gpio_irq_unmask,
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.irq_set_type = st_gpio_irq_set_type,
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.irq_startup = st_gpio_irq_startup,
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.irq_shutdown = st_gpio_irq_shutdown,
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};
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static int st_gpio_irq_domain_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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struct st_gpio_bank *bank = h->host_data;
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irq_set_chip(virq, &st_gpio_irqchip);
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irq_set_handler(virq, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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irq_set_chip_data(virq, bank);
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return 0;
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}
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static struct irq_domain_ops st_gpio_irq_ops = {
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.map = st_gpio_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static int st_gpiolib_register_bank(struct st_pinctrl *info,
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@@ -1219,8 +1378,8 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
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struct pinctrl_gpio_range *range = &bank->range;
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struct device *dev = info->dev;
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int bank_num = of_alias_get_id(np, "gpio");
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struct resource res;
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int err;
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struct resource res, irq_res;
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int gpio_irq = 0, err, i;
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if (of_address_to_resource(np, 0, &res))
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return -ENODEV;
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@@ -1248,6 +1407,51 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
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}
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dev_info(dev, "%s bank added.\n", range->name);
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/**
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* GPIO bank can have one of the two possible types of
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* interrupt-wirings.
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*
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* First type is via irqmux, single interrupt is used by multiple
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* gpio banks. This reduces number of overall interrupts numbers
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* required. All these banks belong to a single pincontroller.
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* _________
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* | |----> [gpio-bank (n) ]
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* | |----> [gpio-bank (n + 1)]
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* [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
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* | |----> [gpio-bank (... )]
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* |_________|----> [gpio-bank (n + 7)]
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*
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* Second type has a dedicated interrupt per each gpio bank.
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*
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* [irqN]----> [gpio-bank (n)]
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*/
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if (!of_irq_to_resource(np, 0, &irq_res)) {
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gpio_irq = irq_res.start;
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irq_set_chained_handler(gpio_irq, st_gpio_irq_handler);
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irq_set_handler_data(gpio_irq, bank);
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}
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if (info->irqmux_base > 0 || gpio_irq > 0) {
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/* Setup IRQ domain */
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bank->domain = irq_domain_add_linear(np,
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ST_GPIO_PINS_PER_BANK,
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&st_gpio_irq_ops, bank);
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if (!bank->domain) {
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dev_err(dev, "Failed to add irq domain for %s\n",
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np->full_name);
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} else {
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for (i = 0; i < ST_GPIO_PINS_PER_BANK; i++) {
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if (irq_create_mapping(bank->domain, i) < 0)
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dev_err(dev,
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"Failed to map IRQ %i\n", i);
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}
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}
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} else {
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dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
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}
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return 0;
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}
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@@ -1276,6 +1480,8 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
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struct device_node *np = pdev->dev.of_node;
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struct device_node *child;
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int grp_index = 0;
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int irq = 0;
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struct resource *res;
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st_pctl_dt_child_count(info, np);
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if (!info->nbanks) {
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@@ -1306,6 +1512,21 @@ static int st_pctl_probe_dt(struct platform_device *pdev,
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}
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info->data = of_match_node(st_pctl_of_match, np)->data;
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irq = platform_get_irq(pdev, 0);
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if (irq > 0) {
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res = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, "irqmux");
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info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(info->irqmux_base))
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return PTR_ERR(info->irqmux_base);
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irq_set_chained_handler(irq, st_gpio_irqmux_handler);
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irq_set_handler_data(irq, info);
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}
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pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
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pdesc = devm_kzalloc(&pdev->dev,
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sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
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