Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too many to enumerate them
all, but at a glance:
New SoCs introduced in this release:
- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
set top boxes and other products.
- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other
on-chip ethernet options.
- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current
high-end mobile SoCs.
It's great to see mainline support for it. So far, you can't do
much with it, since a lot of peripherals are not yet in the DTs
but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC
upstream if the momentum keeps up.
- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive
entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
enabled, we are eagerly awaiting more. So far, basic drivers
such as serial, gpios, PMU and ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and
ethernet enabled, and SMP support is also forthcoming.
- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support
Enhancements to SoCs/platforms (DTS contents, some driver portions
might not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support
New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
ARM: dts: aspeed: Fix hwrng register address
arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
arm64: dts: sprd: Add GPIO and GPIO keys device nodes
arm64: dts: sprd: fix typo in 'remote-endpoint'
arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
arm64: dts: fix regulator property name for wlan pcie endpoint
arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
ARM: dts: pxa3xx: fix MMC clocks
ARM: pxa: dts: add pin definitions for extended GPIOs
ARM: pxa: dts: add gpio-ranges to gpio controller
ARM: dts: ipq8074: Enable few peripherals for hk01 board
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Change the max opp frequency
...
This commit is contained in:
Linus Torvalds
@@ -5,3 +5,7 @@ KERNEL NEW DEPENDENCIES
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v4.3+ Update is needed for custom .config files to make sure
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CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work
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properly.
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v4.18+ Update is needed for custom .config files to make sure
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CONFIG_MMC_SDHCI_OMAP is enabled for all MMC instances
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to work in DRA7 and K2G based boards.
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@@ -25,6 +25,10 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8b";
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Boards with the Amlogic Meson8m2 SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson8m2";
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Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
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Required root node property:
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compatible: "amlogic,meson-gxbb";
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@@ -54,6 +58,8 @@ Board compatible values (alphabetically, grouped by SoC):
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- "hardkernel,odroid-c1" (Meson8b)
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- "tronfy,mxq" (Meson8b)
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- "tronsmart,mxiii-plus" (Meson8m2)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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- "friendlyarm,nanopi-k2" (Meson gxbb)
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@@ -34,6 +34,10 @@ Raspberry Pi 3 Model B
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Required root node properties:
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compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
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Raspberry Pi 3 Model B+
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Required root node properties:
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compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
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Raspberry Pi Compute Module
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Required root node properties:
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compatible = "raspberrypi,compute-module", "brcm,bcm2835";
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@@ -21,8 +21,6 @@ Required root node properties:
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- "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
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- "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
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- "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
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- "samsung,sd5v1" - for Exynos5440-based Samsung board.
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- "samsung,ssdk5440" - for Exynos5440-based Samsung board.
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* Other companies Exynos SoC based
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* FriendlyARM
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@@ -47,6 +47,8 @@ SoCs:
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compatible = "renesas,r8a77970"
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- R-Car V3H (R8A77980)
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compatible = "renesas,r8a77980"
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- R-Car E3 (R8A77990)
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compatible = "renesas,r8a77990"
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- R-Car D3 (R8A77995)
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compatible = "renesas,r8a77995"
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@@ -69,6 +71,8 @@ Boards:
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compatible = "renesas,draak", "renesas,r8a77995"
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- Eagle (RTP0RC77970SEB0010S)
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compatible = "renesas,eagle", "renesas,r8a77970"
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- Ebisu (RTP0RC77990SEB0010S)
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compatible = "renesas,ebisu", "renesas,r8a77990"
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- Genmai (RTK772100BC00000BR)
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compatible = "renesas,genmai", "renesas,r7s72100"
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- GR-Peach (X28A-M01-E/F)
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@@ -80,6 +84,8 @@ Boards:
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compatible = "renesas,h3ulcb", "renesas,r8a7795"
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- Henninger
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compatible = "renesas,henninger", "renesas,r8a7791"
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- iWave Systems RZ/G1C Single Board Computer (iW-RainboW-G23S)
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compatible = "iwave,g23s", "renesas,r8a77470"
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- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
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compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
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- iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
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@@ -110,7 +116,7 @@ Boards:
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compatible = "renesas,salvator-x", "renesas,r8a7795"
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- Salvator-X (RTP0RC7796SIPB0011S)
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compatible = "renesas,salvator-x", "renesas,r8a7796"
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- Salvator-X (RTP0RC7796SIPB0011S (M3N))
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- Salvator-X (RTP0RC7796SIPB0011S (M3-N))
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compatible = "renesas,salvator-x", "renesas,r8a77965"
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- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
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compatible = "renesas,salvator-xs", "renesas,r8a7795"
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@@ -126,6 +132,8 @@ Boards:
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compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
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- Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
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compatible = "renesas,stout", "renesas,r8a7790"
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- V3HSK (Y-ASK-RCAR-V3H-WS10)
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compatible = "renesas,v3hsk", "renesas,r8a77980"
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- V3MSK (Y-ASK-RCAR-V3M-WS10)
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compatible = "renesas,v3msk", "renesas,r8a77970"
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- Wheat (RTP0RC7792ASKB0000JE)
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||||
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@@ -1,18 +0,0 @@
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NVIDIA Tegra30 MC(Memory Controller)
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Required properties:
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- compatible : "nvidia,tegra30-mc"
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- reg : Should contain 4 register ranges(address and length); see the
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example below. Note that the MC registers are interleaved with the
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SMMU registers, and hence must be represented as multiple ranges.
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- interrupts : Should contain MC General interrupt.
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||||
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Example:
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memory-controller {
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compatible = "nvidia,tegra30-mc";
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reg = <0x7000f000 0x010
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0x7000f03c 0x1b4
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0x7000f200 0x028
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0x7000f284 0x17c>;
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interrupts = <0 77 0x04>;
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};
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@@ -10,9 +10,6 @@ Required Properties:
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||||
"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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- reg: physical base address of the clock controller and length of memory
|
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mapped region.
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|
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- #clock-cells: should be 1.
|
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|
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Each clock is assigned an identifier and client nodes can use this identifier
|
||||
@@ -20,13 +17,22 @@ to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
|
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used in device tree sources.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
|
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"amlogic,meson-axg-hhi-sysctrl"
|
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- reg: base address and size of the HHI system control register space.
|
||||
|
||||
Example: Clock controller node:
|
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clkc: clock-controller@c883c000 {
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sysctrl: system-controller@0 {
|
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compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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#clock-cells = <1>;
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compatible = "amlogic,gxbb-clkc";
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reg = <0x0 0xc883c000 0x0 0x3db>;
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};
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};
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|
||||
Example: UART controller node that consumes the clock generated by the clock
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||||
controller:
|
||||
|
||||
@@ -6,11 +6,21 @@ Required properties:
|
||||
example below. Note that the MC registers are interleaved with the
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||||
GART registers, and hence must be represented as multiple ranges.
|
||||
- interrupts : Should contain MC General interrupt.
|
||||
- #reset-cells : Should be 1. This cell represents memory client module ID.
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The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
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or in the TRM documentation.
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Example:
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memory-controller@7000f000 {
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mc: memory-controller@7000f000 {
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compatible = "nvidia,tegra20-mc";
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reg = <0x7000f000 0x024
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0x7000f03c 0x3c4>;
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interrupts = <0 77 0x04>;
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||||
#reset-cells = <1>;
|
||||
};
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||||
|
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video-codec@6001a000 {
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compatible = "nvidia,tegra20-vde";
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||||
...
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resets = <&mc TEGRA20_MC_RESET_VDE>;
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};
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||||
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@@ -12,6 +12,9 @@ Required properties:
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||||
- clock-names: Must include the following entries:
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- mc: the module's clock input
|
||||
- interrupts: The interrupt outputs from the controller.
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||||
- #reset-cells : Should be 1. This cell represents memory client module ID.
|
||||
The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
|
||||
or in the TRM documentation.
|
||||
|
||||
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
|
||||
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
|
||||
@@ -72,12 +75,14 @@ Example SoC include file:
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||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#iommu-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
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sdhci@700b0000 {
|
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compatible = "nvidia,tegra124-sdhci";
|
||||
...
|
||||
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
|
||||
resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -4,6 +4,7 @@ Required properties:
|
||||
- compatible: Should be one of the following:
|
||||
"allwinner,sun4i-a10-sid"
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||||
"allwinner,sun7i-a20-sid"
|
||||
"allwinner,sun8i-a83t-sid"
|
||||
"allwinner,sun8i-h3-sid"
|
||||
"allwinner,sun50i-a64-sid"
|
||||
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
Command DB
|
||||
---------
|
||||
|
||||
Command DB is a database that provides a mapping between resource key and the
|
||||
resource address for a system resource managed by a remote processor. The data
|
||||
is stored in a shared memory region and is loaded by the remote processor.
|
||||
|
||||
Some of the Qualcomm Technologies Inc SoC's have hardware accelerators for
|
||||
controlling shared resources. Depending on the board configuration the shared
|
||||
resource properties may change. These properties are dynamically probed by the
|
||||
remote processor and made available in the shared memory.
|
||||
|
||||
The bindings for Command DB is specified in the reserved-memory section in
|
||||
devicetree. The devicetree representation of the command DB driver should be:
|
||||
|
||||
Properties:
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Should be "qcom,cmd-db"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop encoded array>
|
||||
Definition: The register address that points to the actual location of
|
||||
the Command DB in memory.
|
||||
|
||||
Example:
|
||||
|
||||
reserved-memory {
|
||||
[...]
|
||||
reserved-memory@85fe0000 {
|
||||
reg = <0x0 0x85fe0000 0x0 0x20000>;
|
||||
compatible = "qcom,cmd-db";
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
@@ -14,11 +14,16 @@ Optional properties:
|
||||
- clocks : phandle to clock-controller plus clock-specifier pair
|
||||
- clock-names : "ipsec" as a clock name
|
||||
|
||||
Optional properties:
|
||||
|
||||
- interrupts: specify the interrupt for the RNG block
|
||||
|
||||
Example:
|
||||
|
||||
rng {
|
||||
compatible = "brcm,bcm2835-rng";
|
||||
reg = <0x7e104000 0x10>;
|
||||
compatible = "brcm,bcm2835-rng";
|
||||
reg = <0x7e104000 0x10>;
|
||||
interrupts = <2 29>;
|
||||
};
|
||||
|
||||
rng@18033000 {
|
||||
|
||||
119
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
Normal file
119
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
Normal file
@@ -0,0 +1,119 @@
|
||||
Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
|
||||
|
||||
Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
|
||||
is a programmable module for supporting a wide range of serial interfaces
|
||||
like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
|
||||
Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
|
||||
Wrapper controller is modeled as a node with zero or more child nodes each
|
||||
representing a serial engine.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,geni-se-qup".
|
||||
- reg: Must contain QUP register address and length.
|
||||
- clock-names: Must contain "m-ahb" and "s-ahb".
|
||||
- clocks: AHB clocks needed by the device.
|
||||
|
||||
Required properties if child node exists:
|
||||
- #address-cells: Must be <1> for Serial Engine Address
|
||||
- #size-cells: Must be <1> for Serial Engine Address Size
|
||||
- ranges: Must be present
|
||||
|
||||
Properties for children:
|
||||
|
||||
A GENI based QUP wrapper controller node can contain 0 or more child nodes
|
||||
representing serial devices. These serial devices can be a QCOM UART, I2C
|
||||
controller, SPI controller, or some combination of aforementioned devices.
|
||||
Please refer below the child node definitions for the supported serial
|
||||
interface protocols.
|
||||
|
||||
Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,geni-i2c".
|
||||
- reg: Must contain QUP register address and length.
|
||||
- interrupts: Must contain I2C interrupt.
|
||||
- clock-names: Must contain "se".
|
||||
- clocks: Serial engine core clock needed by the device.
|
||||
- #address-cells: Must be <1> for I2C device address.
|
||||
- #size-cells: Must be <0> as I2C addresses have no size component.
|
||||
|
||||
Optional property:
|
||||
- clock-frequency: Desired I2C bus clock frequency in Hz.
|
||||
When missing default to 400000Hz.
|
||||
|
||||
Child nodes should conform to I2C bus binding as described in i2c.txt.
|
||||
|
||||
Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "qcom,geni-debug-uart".
|
||||
- reg: Must contain UART register location and length.
|
||||
- interrupts: Must contain UART core interrupts.
|
||||
- clock-names: Must contain "se".
|
||||
- clocks: Serial engine core clock needed by the device.
|
||||
|
||||
Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain "qcom,geni-spi".
|
||||
- reg: Must contain SPI register location and length.
|
||||
- interrupts: Must contain SPI controller interrupts.
|
||||
- clock-names: Must contain "se".
|
||||
- clocks: Serial engine core clock needed by the device.
|
||||
- spi-max-frequency: Specifies maximum SPI clock frequency, units - Hz.
|
||||
- #address-cells: Must be <1> to define a chip select address on
|
||||
the SPI bus.
|
||||
- #size-cells: Must be <0>.
|
||||
|
||||
SPI slave nodes must be children of the SPI master node and conform to SPI bus
|
||||
binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
|
||||
|
||||
Example:
|
||||
geniqup@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x8c0000 0x6000>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
i2c0: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0xa94000 0x4000>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qup_1_i2c_5_active>;
|
||||
pinctrl-1 = <&qup_1_i2c_5_sleep>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
uart0: serial@a88000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0xa88000 0x7000>;
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qup_1_uart_3_active>;
|
||||
pinctrl-1 = <&qup_1_uart_3_sleep>;
|
||||
};
|
||||
|
||||
spi0: spi@a84000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0xa84000 0x4000>;
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se";
|
||||
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qup_1_spi_2_active>;
|
||||
pinctrl-1 = <&qup_1_spi_2_sleep>;
|
||||
spi-max-frequency = <19200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
}
|
||||
@@ -22,6 +22,10 @@ Required Properties:
|
||||
|
||||
- "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
|
||||
- "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
|
||||
- "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
|
||||
- "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743.
|
||||
- "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745.
|
||||
- "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745.
|
||||
- "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790.
|
||||
- "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790.
|
||||
- "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791.
|
||||
@@ -31,10 +35,12 @@ Required Properties:
|
||||
- "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794.
|
||||
- "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794.
|
||||
|
||||
- "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2.
|
||||
- "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2.
|
||||
These are fallbacks for r8a73a4 and all the R-Car Gen2
|
||||
entries listed above.
|
||||
- "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2
|
||||
and RZ/G1.
|
||||
- "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2
|
||||
and RZ/G1.
|
||||
These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries
|
||||
listed above.
|
||||
|
||||
- reg: base address and length of the registers block for the timer module.
|
||||
- interrupts: interrupt-specifier for the timer, one per channel.
|
||||
|
||||
@@ -58,6 +58,7 @@ bosch Bosch Sensortec GmbH
|
||||
boundary Boundary Devices Inc.
|
||||
brcm Broadcom Corporation
|
||||
buffalo Buffalo, Inc.
|
||||
bticino Bticino International
|
||||
calxeda Calxeda
|
||||
capella Capella Microsystems, Inc
|
||||
cascoda Cascoda, Ltd.
|
||||
@@ -285,6 +286,7 @@ pine64 Pine64
|
||||
pixcir PIXCIR MICROELECTRONICS Co., Ltd
|
||||
plathome Plat'Home Co., Ltd.
|
||||
plda PLDA
|
||||
portwell Portwell Inc.
|
||||
poslab Poslab Technology Co., Ltd.
|
||||
powervr PowerVR (deprecated, use img)
|
||||
probox2 PROBOX2 (by W2COMP Co., Ltd.)
|
||||
|
||||
Reference in New Issue
Block a user