tools/memory-model: Rename litmus tests to comply to norm7
norm7 produces the 'normalized' name of a litmus test, when the test can be generated from a single cycle that passes through each process exactly once. The commit renames such tests in order to comply to the naming scheme implemented by this tool. Signed-off-by: Andrea Parri <andrea.parri@amarulasolutions.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Cc: Akira Yokosawa <akiyks@gmail.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: David Howells <dhowells@redhat.com> Cc: Jade Alglave <j.alglave@ucl.ac.uk> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Luc Maranget <luc.maranget@inria.fr> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arch@vger.kernel.org Cc: parri.andrea@gmail.com Link: http://lkml.kernel.org/r/20180716180605.16115-14-paulmck@linux.vnet.ibm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Ingo Molnar

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commit
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@@ -126,7 +126,7 @@ However, it is not necessarily the case that accesses ordered by
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locking will be seen as ordered by CPUs not holding that lock.
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Consider this example:
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/* See Z6.0+pooncelock+pooncelock+pombonce.litmus. */
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/* See Z6.0+pooncerelease+poacquirerelease+fencembonceonce.litmus. */
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void CPU0(void)
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{
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spin_lock(&mylock);
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@@ -292,7 +292,7 @@ and to use smp_load_acquire() instead of smp_rmb(). However, the older
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smp_wmb() and smp_rmb() APIs are still heavily used, so it is important
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to understand their use cases. The general approach is shown below:
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/* See MP+wmbonceonce+rmbonceonce.litmus. */
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/* See MP+fencewmbonceonce+fencermbonceonce.litmus. */
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void CPU0(void)
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{
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WRITE_ONCE(x, 1);
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@@ -360,7 +360,7 @@ can be seen in the LB+poonceonces.litmus litmus test.
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One way of avoiding the counter-intuitive outcome is through the use of a
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control dependency paired with a full memory barrier:
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/* See LB+ctrlonceonce+mbonceonce.litmus. */
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/* See LB+fencembonceonce+ctrlonceonce.litmus. */
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void CPU0(void)
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{
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r0 = READ_ONCE(x);
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@@ -476,7 +476,7 @@ that one CPU first stores to one variable and then loads from a second,
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while another CPU stores to the second variable and then loads from the
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first. Preserving order requires nothing less than full barriers:
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/* See SB+mbonceonces.litmus. */
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/* See SB+fencembonceonces.litmus. */
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void CPU0(void)
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{
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WRITE_ONCE(x, 1);
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