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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Browse Source 
Conflicts:
	drivers/net/ethernet/rocker/rocker.c

The rocker commit was two overlapping changes, one to rename
the ->vport member to ->pport, and another making the bitmask
expression use '1ULL' instead of plain '1'.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2015-03-03 21:16:48 -05:00
parent b97526f3ff a6c5170d1e
commit 71a83a6db6
1279 changed files with 49656 additions and 20344 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
arch/alpha/include/asm/uaccess.h
View File

@@ -27,7 +27,7 @@
#define get_ds() (KERNEL_DS)
#define set_fs(x) (current_thread_info()->addr_limit = (x))
#define segment_eq(a,b) ((a).seg == (b).seg)
#define segment_eq(a, b) ((a).seg == (b).seg)
/*
* Is a address valid? This does a straightforward calculation rather
@@ -39,13 +39,13 @@
* - AND "addr+size" doesn't have any high-bits set
* - OR we are in kernel mode.
*/
#define __access_ok(addr,size,segment) \
#define __access_ok(addr, size, segment) \
(((segment).seg & (addr | size | (addr+size))) == 0)
#define access_ok(type,addr,size) \
#define access_ok(type, addr, size) \
({ \
__chk_user_ptr(addr); \
__access_ok(((unsigned long)(addr)),(size),get_fs()); \
__access_ok(((unsigned long)(addr)), (size), get_fs()); \
})
/*
@@ -60,20 +60,20 @@
* (a) re-use the arguments for side effects (sizeof/typeof is ok)
* (b) require any knowledge of processes at this stage
*/
#define put_user(x,ptr) \
__put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)),get_fs())
#define get_user(x,ptr) \
__get_user_check((x),(ptr),sizeof(*(ptr)),get_fs())
#define put_user(x, ptr) \
__put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)), get_fs())
#define get_user(x, ptr) \
__get_user_check((x), (ptr), sizeof(*(ptr)), get_fs())
/*
* The "__xxx" versions do not do address space checking, useful when
* doing multiple accesses to the same area (the programmer has to do the
* checks by hand with "access_ok()")
*/
#define __put_user(x,ptr) \
__put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
#define __get_user(x,ptr) \
__get_user_nocheck((x),(ptr),sizeof(*(ptr)))
#define __put_user(x, ptr) \
__put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
#define __get_user(x, ptr) \
__get_user_nocheck((x), (ptr), sizeof(*(ptr)))
/*
* The "lda %1, 2b-1b(%0)" bits are magic to get the assembler to
@@ -84,7 +84,7 @@
extern void __get_user_unknown(void);
#define __get_user_nocheck(x,ptr,size) \
#define __get_user_nocheck(x, ptr, size) \
({ \
long __gu_err = 0; \
unsigned long __gu_val; \
@@ -96,16 +96,16 @@ extern void __get_user_unknown(void);
case 8: __get_user_64(ptr); break; \
default: __get_user_unknown(); break; \
} \
(x) = (__typeof__(*(ptr))) __gu_val; \
(x) = (__force __typeof__(*(ptr))) __gu_val; \
__gu_err; \
})
#define __get_user_check(x,ptr,size,segment) \
#define __get_user_check(x, ptr, size, segment) \
({ \
long __gu_err = -EFAULT; \
unsigned long __gu_val = 0; \
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
if (__access_ok((unsigned long)__gu_addr,size,segment)) { \
if (__access_ok((unsigned long)__gu_addr, size, segment)) { \
__gu_err = 0; \
switch (size) { \
case 1: __get_user_8(__gu_addr); break; \
@@ -115,7 +115,7 @@ extern void __get_user_unknown(void);
default: __get_user_unknown(); break; \
} \
} \
(x) = (__typeof__(*(ptr))) __gu_val; \
(x) = (__force __typeof__(*(ptr))) __gu_val; \
__gu_err; \
})
@@ -201,31 +201,31 @@ struct __large_struct { unsigned long buf[100]; };
extern void __put_user_unknown(void);
#define __put_user_nocheck(x,ptr,size) \
#define __put_user_nocheck(x, ptr, size) \
({ \
long __pu_err = 0; \
__chk_user_ptr(ptr); \
switch (size) { \
case 1: __put_user_8(x,ptr); break; \
case 2: __put_user_16(x,ptr); break; \
case 4: __put_user_32(x,ptr); break; \
case 8: __put_user_64(x,ptr); break; \
case 1: __put_user_8(x, ptr); break; \
case 2: __put_user_16(x, ptr); break; \
case 4: __put_user_32(x, ptr); break; \
case 8: __put_user_64(x, ptr); break; \
default: __put_user_unknown(); break; \
} \
__pu_err; \
})
#define __put_user_check(x,ptr,size,segment) \
#define __put_user_check(x, ptr, size, segment) \
({ \
long __pu_err = -EFAULT; \
__typeof__(*(ptr)) __user *__pu_addr = (ptr); \
if (__access_ok((unsigned long)__pu_addr,size,segment)) { \
if (__access_ok((unsigned long)__pu_addr, size, segment)) { \
__pu_err = 0; \
switch (size) { \
case 1: __put_user_8(x,__pu_addr); break; \
case 2: __put_user_16(x,__pu_addr); break; \
case 4: __put_user_32(x,__pu_addr); break; \
case 8: __put_user_64(x,__pu_addr); break; \
case 1: __put_user_8(x, __pu_addr); break; \
case 2: __put_user_16(x, __pu_addr); break; \
case 4: __put_user_32(x, __pu_addr); break; \
case 8: __put_user_64(x, __pu_addr); break; \
default: __put_user_unknown(); break; \
} \
} \
@@ -237,7 +237,7 @@ extern void __put_user_unknown(void);
* instead of writing: this is because they do not write to
* any memory gcc knows about, so there are no aliasing issues
*/
#define __put_user_64(x,addr) \
#define __put_user_64(x, addr) \
__asm__ __volatile__("1: stq %r2,%1\n" \
"2:\n" \
".section __ex_table,\"a\"\n" \
@@ -247,7 +247,7 @@ __asm__ __volatile__("1: stq %r2,%1\n" \
: "=r"(__pu_err) \
: "m" (__m(addr)), "rJ" (x), "0"(__pu_err))
#define __put_user_32(x,addr) \
#define __put_user_32(x, addr) \
__asm__ __volatile__("1: stl %r2,%1\n" \
"2:\n" \
".section __ex_table,\"a\"\n" \
@@ -260,7 +260,7 @@ __asm__ __volatile__("1: stl %r2,%1\n" \
#ifdef __alpha_bwx__
/* Those lucky bastards with ev56 and later CPUs can do byte/word moves. */
#define __put_user_16(x,addr) \
#define __put_user_16(x, addr) \
__asm__ __volatile__("1: stw %r2,%1\n" \
"2:\n" \
".section __ex_table,\"a\"\n" \
@@ -270,7 +270,7 @@ __asm__ __volatile__("1: stw %r2,%1\n" \
: "=r"(__pu_err) \
: "m"(__m(addr)), "rJ"(x), "0"(__pu_err))
#define __put_user_8(x,addr) \
#define __put_user_8(x, addr) \
__asm__ __volatile__("1: stb %r2,%1\n" \
"2:\n" \
".section __ex_table,\"a\"\n" \
@@ -283,7 +283,7 @@ __asm__ __volatile__("1: stb %r2,%1\n" \
/* Unfortunately, we can't get an unaligned access trap for the sub-word
write, so we have to do a general unaligned operation. */
#define __put_user_16(x,addr) \
#define __put_user_16(x, addr) \
{ \
long __pu_tmp1, __pu_tmp2, __pu_tmp3, __pu_tmp4; \
__asm__ __volatile__( \
@@ -308,13 +308,13 @@ __asm__ __volatile__("1: stb %r2,%1\n" \
" .long 4b - .\n" \
" lda $31, 5b-4b(%0)\n" \
".previous" \
: "=r"(__pu_err), "=&r"(__pu_tmp1), \
"=&r"(__pu_tmp2), "=&r"(__pu_tmp3), \
: "=r"(__pu_err), "=&r"(__pu_tmp1), \
"=&r"(__pu_tmp2), "=&r"(__pu_tmp3), \
"=&r"(__pu_tmp4) \
: "r"(addr), "r"((unsigned long)(x)), "0"(__pu_err)); \
}
#define __put_user_8(x,addr) \
#define __put_user_8(x, addr) \
{ \
long __pu_tmp1, __pu_tmp2; \
__asm__ __volatile__( \
@@ -330,7 +330,7 @@ __asm__ __volatile__("1: stb %r2,%1\n" \
" .long 2b - .\n" \
" lda $31, 3b-2b(%0)\n" \
".previous" \
: "=r"(__pu_err), \
: "=r"(__pu_err), \
"=&r"(__pu_tmp1), "=&r"(__pu_tmp2) \
: "r"((unsigned long)(x)), "r"(addr), "0"(__pu_err)); \
}
@@ -366,7 +366,7 @@ __copy_tofrom_user_nocheck(void *to, const void *from, long len)
: "=r" (__cu_len), "=r" (__cu_from), "=r" (__cu_to)
: __module_address(__copy_user)
"0" (__cu_len), "1" (__cu_from), "2" (__cu_to)
: "$1","$2","$3","$4","$5","$28","memory");
: "$1", "$2", "$3", "$4", "$5", "$28", "memory");
return __cu_len;
}
@@ -379,15 +379,15 @@ __copy_tofrom_user(void *to, const void *from, long len, const void __user *vali
return len;
}
#define __copy_to_user(to,from,n) \
#define __copy_to_user(to, from, n) \
({ \
__chk_user_ptr(to); \
__copy_tofrom_user_nocheck((__force void *)(to),(from),(n)); \
__copy_tofrom_user_nocheck((__force void *)(to), (from), (n)); \
})
#define __copy_from_user(to,from,n) \
#define __copy_from_user(to, from, n) \
({ \
__chk_user_ptr(from); \
__copy_tofrom_user_nocheck((to),(__force void *)(from),(n)); \
__copy_tofrom_user_nocheck((to), (__force void *)(from), (n)); \
})
#define __copy_to_user_inatomic __copy_to_user
@@ -418,7 +418,7 @@ __clear_user(void __user *to, long len)
: "=r"(__cl_len), "=r"(__cl_to)
: __module_address(__do_clear_user)
"0"(__cl_len), "1"(__cl_to)
: "$1","$2","$3","$4","$5","$28","memory");
: "$1", "$2", "$3", "$4", "$5", "$28", "memory");
return __cl_len;
}

2
arch/arc/boot/dts/abilis_tb10x.dtsi
View File

@@ -112,7 +112,7 @@
chan_allocation_order = <0>;
chan_priority = <1>;
block_size = <0x7ff>;
data_width = <2 0 0 0>;
data_width = <2>;
clocks = <&ahb_clk>;
clock-names = "hclk";
};

1
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@@ -195,6 +195,7 @@
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
&usb1 {

25
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@@ -133,20 +133,6 @@
>;
};
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};
i2c1_pins_sleep: i2c1_pins_sleep {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
>;
};
mmc1_pins_default: pinmux_mmc1_pins_default {
pinctrl-single,pins = <
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
@@ -254,7 +240,7 @@
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c0_pins_default>;
pinctrl-1 = <&i2c0_pins_default>;
pinctrl-1 = <&i2c0_pins_sleep>;
clock-frequency = <400000>;
at24@50 {
@@ -262,17 +248,10 @@
pagesize = <64>;
reg = <0x50>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-1 = <&i2c1_pins_default>;
clock-frequency = <400000>;
tps: tps62362@60 {
compatible = "ti,tps62362";
reg = <0x60>;
regulator-name = "VDD_MPU";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1330000>;

8
arch/arm/boot/dts/am57xx-beagle-x15.dts
View File

@@ -549,14 +549,6 @@
pinctrl-0 = <&usb1_pins>;
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb2 {
dr_mode = "peripheral";
};

20
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@@ -70,6 +70,26 @@
};
};
i2c0: i2c@18008000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x18008000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@1800b000 {
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
reg = <0x1800b000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
clock-frequency = <100000>;
status = "disabled";
};
uart0: serial@18020000 {
compatible = "snps,dw-apb-uart";
reg = <0x18020000 0x100>;

5
arch/arm/boot/dts/bcm63138.dtsi
View File

@@ -66,8 +66,9 @@
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-sets = <16>;
cache-size = <0x80000>;
cache-size = <524288>;
cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};

25
arch/arm/boot/dts/dm8168-evm.dts
View File

@@ -35,6 +35,18 @@
DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
>;
};
usb0_pins: pinmux_usb0_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
>;
};
usb1_pins: pinmux_usb0_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */
>;
};
};
&i2c1 {
@@ -127,3 +139,16 @@
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
};
/* At least dm8168-evm rev c won't support multipoint, later may */
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins>;
mentor,multipoint = <0>;
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
mentor,multipoint = <0>;
};

34
arch/arm/boot/dts/dm816x.dtsi
View File

@@ -97,10 +97,31 @@
/* Device Configuration Registers */
scm_conf: syscon@600 {
compatible = "syscon";
compatible = "syscon", "simple-bus";
reg = <0x600 0x110>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x110>;
usb_phy0: usb-phy@20 {
compatible = "ti,dm8168-usb-phy";
reg = <0x20 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};
usb_phy1: usb-phy@28 {
compatible = "ti,dm8168-usb-phy";
reg = <0x28 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};
};
scrm_clocks: clocks {
@@ -357,7 +378,10 @@
reg-names = "mc", "control";
interrupts = <18>;
interrupt-names = "mc";
dr_mode = "otg";
dr_mode = "host";
interface-type = <0>;
phys = <&usb_phy0>;
phy-names = "usb2-phy";
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;
@@ -366,13 +390,15 @@
usb1: usb@47401800 {
compatible = "ti,musb-am33xx";
status = "disabled";
reg = <0x47401c00 0x400
0x47401800 0x200>;
reg-names = "mc", "control";
interrupts = <19>;
interrupt-names = "mc";
dr_mode = "otg";
dr_mode = "host";
interface-type = <0>;
phys = <&usb_phy1>;
phy-names = "usb2-phy";
mentor,multipoint = <1>;
mentor,num-eps = <16>;
mentor,ram-bits = <12>;

8
arch/arm/boot/dts/dra7-evm.dts
View File

@@ -543,14 +543,6 @@
};
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";

8
arch/arm/boot/dts/dra7.dtsi
View File

@@ -249,8 +249,8 @@
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
dma-channels = <32>;
dma-requests = <127>;
};
gpio1: gpio@4ae10000 {
@@ -1090,8 +1090,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_sata>;
clocks = <&sys_clkin1>;
clock-names = "sysclk";
clocks = <&sys_clkin1>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};

8
arch/arm/boot/dts/dra72-evm.dts
View File

@@ -380,14 +380,6 @@
phy-supply = <&ldo4_reg>;
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";

4
arch/arm/boot/dts/omap2.dtsi
View File

@@ -87,8 +87,8 @@
<14>,
<15>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <64>;
dma-channels = <32>;
dma-requests = <64>;
};
i2c1: i2c@48070000 {

9
arch/arm/boot/dts/omap3-n900.dts
View File

@@ -16,6 +16,13 @@
model = "Nokia N900";
compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
aliases {
i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
};
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
@@ -704,7 +711,7 @@
compatible = "smsc,lan91c94";
interrupt-parent = <&gpio2>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */
reg = <1 0 0xf>; /* 16 byte IO range */
bank-width = <2>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_pins>;

4
arch/arm/boot/dts/omap3.dtsi
View File

@@ -155,8 +155,8 @@
<14>,
<15>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <96>;
dma-channels = <32>;
dma-requests = <96>;
};
omap3_pmx_core: pinmux@48002030 {

4
arch/arm/boot/dts/omap4.dtsi
View File

@@ -223,8 +223,8 @@
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
dma-channels = <32>;
dma-requests = <127>;
};
gpio1: gpio@4a310000 {

8
arch/arm/boot/dts/omap5.dtsi
View File

@@ -238,8 +238,8 @@
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
dma-channels = <32>;
dma-requests = <127>;
};
gpio1: gpio@4ae10000 {
@@ -929,8 +929,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_sata>;
clocks = <&sys_clkin>;
clock-names = "sysclk";
clocks = <&sys_clkin>, <&sata_ref_clk>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};
};

4
arch/arm/boot/dts/spear13xx.dtsi
View File

@@ -117,7 +117,7 @@
chan_priority = <1>;
block_size = <0xfff>;
dma-masters = <2>;
data_width = <3 3 0 0>;
data_width = <3 3>;
};
dma@eb000000 {
@@ -133,7 +133,7 @@
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
data_width = <3 3 0 0>;
data_width = <3 3>;
};
fsmc: flash@b0000000 {

72
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@@ -294,35 +294,43 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc3";
clock-output-names = "mmc3",
"mmc3_output",
"mmc3_sample";
};
ts_clk: clk@01c20098 {
@@ -468,8 +476,14 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <32>;
status = "disabled";
};
@@ -477,8 +491,14 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb_gates 9>, <&mmc1_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <33>;
status = "disabled";
};
@@ -486,8 +506,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <34>;
status = "disabled";
};
@@ -495,8 +521,14 @@
mmc3: mmc@01c12000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&ahb_gates 11>, <&mmc3_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 11>,
<&mmc3_clk 0>,
<&mmc3_clk 1>,
<&mmc3_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <35>;
status = "disabled";
};

54
arch/arm/boot/dts/sun5i-a10s.dtsi
View File

@@ -218,27 +218,33 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
ts_clk: clk@01c20098 {
@@ -368,8 +374,14 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <32>;
status = "disabled";
};
@@ -377,8 +389,14 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb_gates 9>, <&mmc1_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <33>;
status = "disabled";
};
@@ -386,8 +404,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <34>;
status = "disabled";
};

44
arch/arm/boot/dts/sun5i-a13.dtsi
View File

@@ -257,27 +257,33 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
ts_clk: clk@01c20098 {
@@ -391,8 +397,14 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <32>;
status = "disabled";
};
@@ -400,8 +412,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <34>;
status = "disabled";
};

86
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@@ -190,19 +190,11 @@
clock-output-names = "axi";
};
ahb1_mux: ahb1_mux@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1_mux";
};
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-ahb-clk";
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1_mux>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
@@ -265,35 +257,43 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc0";
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc1";
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc2";
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc3";
clock-output-names = "mmc3",
"mmc3_output",
"mmc3_sample";
};
spi0_clk: clk@01c200a0 {
@@ -383,15 +383,21 @@
#dma-cells = <1>;
/* DMA controller requires AHB1 clocked from PLL6 */
assigned-clocks = <&ahb1_mux>;
assigned-clocks = <&ahb1>;
assigned-clock-parents = <&pll6 0>;
};
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb1_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 8>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -401,8 +407,14 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb1_gates 9>, <&mmc1_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 9>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -412,8 +424,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb1_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 10>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -423,8 +441,14 @@
mmc3: mmc@01c12000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&ahb1_gates 11>, <&mmc3_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 11>,
<&mmc3_clk 0>,
<&mmc3_clk 1>,
<&mmc3_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 11>;
reset-names = "ahb";
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

72
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@@ -337,35 +337,43 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0";
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1";
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2";
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
mmc3_clk: clk@01c20094 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc3";
clock-output-names = "mmc3",
"mmc3_output",
"mmc3_sample";
};
ts_clk: clk@01c20098 {
@@ -583,8 +591,14 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -592,8 +606,14 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb_gates 9>, <&mmc1_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -601,8 +621,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -610,8 +636,14 @@
mmc3: mmc@01c12000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&ahb_gates 11>, <&mmc3_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb_gates 11>,
<&mmc3_clk 0>,
<&mmc3_clk 1>,
<&mmc3_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

96
arch/arm/boot/dts/sun8i-a23.dtsi
View File

@@ -119,11 +119,19 @@
};
/* dummy clock until actually implemented */
pll6: pll6_clk {
pll5: pll5_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <600000000>;
clock-output-names = "pll6";
clock-frequency = <0>;
clock-output-names = "pll5";
};
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6", "pll6x2";
};
cpu: cpu_clk@01c20050 {
@@ -149,19 +157,11 @@
clock-output-names = "axi";
};
ahb1_mux: ahb1_mux_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
clock-output-names = "ahb1_mux";
};
ahb1: ahb1_clk@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-ahb-clk";
compatible = "allwinner,sun6i-a31-ahb1-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1_mux>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
clock-output-names = "ahb1";
};
@@ -202,7 +202,7 @@
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
clock-output-names = "apb2";
};
@@ -218,27 +218,41 @@
};
mmc0_clk: clk@01c20088 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6>;
clock-output-names = "mmc0";
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6>;
clock-output-names = "mmc1";
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6>;
clock-output-names = "mmc2";
clocks = <&osc24M>, <&pll6 0>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
};
@@ -260,8 +274,14 @@
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb1_gates 8>, <&mmc0_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 8>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -271,8 +291,14 @@
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb1_gates 9>, <&mmc1_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 9>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,8 +308,14 @@
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb1_gates 10>, <&mmc2_clk>;
clock-names = "ahb", "mmc";
clocks = <&ahb1_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
resets = <&ahb1_rst 10>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

82
arch/arm/configs/multi_v7_defconfig
View File

@@ -62,6 +62,17 @@ CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
CONFIG_ARCH_EXYNOS=y
CONFIG_EXYNOS5420_MCPM=y
CONFIG_ARCH_SHMOBILE_MULTI=y
CONFIG_ARCH_EMEV2=y
CONFIG_ARCH_R7S72100=y
CONFIG_ARCH_R8A73A4=y
CONFIG_ARCH_R8A7740=y
CONFIG_ARCH_R8A7779=y
CONFIG_ARCH_R8A7790=y
CONFIG_ARCH_R8A7791=y
CONFIG_ARCH_R8A7794=y
CONFIG_ARCH_SH73A0=y
CONFIG_MACH_MARZEN=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_SIRF=y
CONFIG_ARCH_TEGRA=y
@@ -84,6 +95,8 @@ CONFIG_PCI_KEYSTONE=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MVEBU=y
CONFIG_PCI_TEGRA=y
CONFIG_PCI_RCAR_GEN2=y
CONFIG_PCI_RCAR_GEN2_PCIE=y
CONFIG_PCIEPORTBUS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=8
@@ -130,6 +143,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=64
CONFIG_OMAP_OCP2SCP=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
@@ -157,6 +171,7 @@ CONFIG_AHCI_SUNXI=y
CONFIG_AHCI_TEGRA=y
CONFIG_SATA_HIGHBANK=y
CONFIG_SATA_MV=y
CONFIG_SATA_RCAR=y
CONFIG_NETDEVICES=y
CONFIG_HIX5HD2_GMAC=y
CONFIG_SUN4I_EMAC=y
@@ -167,14 +182,17 @@ CONFIG_MV643XX_ETH=y
CONFIG_MVNETA=y
CONFIG_KS8851=y
CONFIG_R8169=y
CONFIG_SH_ETH=y
CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y
CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y
CONFIG_AT803X_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_ICPLUS_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_USB_PEGASUS=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_SMSC75XX=y
@@ -192,15 +210,18 @@ CONFIG_KEYBOARD_CROS_EC=y
CONFIG_MOUSE_PS2_ELANTECH=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ATMEL_MXT=y
CONFIG_TOUCHSCREEN_ST1232=m
CONFIG_TOUCHSCREEN_STMPE=y
CONFIG_TOUCHSCREEN_SUN4I=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_MPU3050=y
CONFIG_INPUT_AXP20X_PEK=y
CONFIG_INPUT_ADXL34X=m
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_EM=y
CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -213,6 +234,9 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
CONFIG_SERIAL_TEGRA=y
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=20
CONFIG_SERIAL_SH_SCI_CONSOLE=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SERIAL_VT8500=y
@@ -233,19 +257,26 @@ CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_MUX_PINCTRL=y
CONFIG_I2C_CADENCE=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=m
CONFIG_I2C_EXYNOS5=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_RIIC=y
CONFIG_I2C_S3C2410=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_I2C_SIRF=y
CONFIG_I2C_TEGRA=y
CONFIG_I2C_ST=y
CONFIG_SPI=y
CONFIG_I2C_TEGRA=y
CONFIG_I2C_XILINX=y
CONFIG_SPI_DAVINCI=y
CONFIG_I2C_RCAR=y
CONFIG_SPI=y
CONFIG_SPI_CADENCE=y
CONFIG_SPI_DAVINCI=y
CONFIG_SPI_OMAP24XX=y
CONFIG_SPI_ORION=y
CONFIG_SPI_PL022=y
CONFIG_SPI_RSPI=y
CONFIG_SPI_SH_MSIOF=m
CONFIG_SPI_SH_HSPI=y
CONFIG_SPI_SIRF=y
CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y
@@ -259,12 +290,15 @@ CONFIG_PINCTRL_PALMAS=y
CONFIG_PINCTRL_APQ8084=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_DAVINCI=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_EM=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_XILINX=y
CONFIG_GPIO_ZYNQ=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_PALMAS=y
CONFIG_GPIO_SYSCON=y
@@ -276,10 +310,12 @@ CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_KEYSTONE=y
CONFIG_POWER_RESET_SUN6I=y
CONFIG_POWER_RESET_RMOBILE=y
CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y
CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y
CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_DAVINCI_WATCHDOG
CONFIG_ST_THERMAL_SYSCFG=y
@@ -290,6 +326,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_ORION_WATCHDOG=y
CONFIG_SUNXI_WATCHDOG=y
CONFIG_MESON_WATCHDOG=y
CONFIG_MFD_AS3711=y
CONFIG_MFD_AS3722=y
CONFIG_MFD_BCM590XX=y
CONFIG_MFD_AXP20X=y
@@ -304,13 +341,16 @@ CONFIG_MFD_TPS65090=y
CONFIG_MFD_TPS6586X=y
CONFIG_MFD_TPS65910=y
CONFIG_REGULATOR_AB8500=y
CONFIG_REGULATOR_AS3711=y
CONFIG_REGULATOR_AS3722=y
CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_BCM590XX=y
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MFD_SYSCON=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_REGULATOR_MAX8907=y
CONFIG_REGULATOR_MAX8973=y
CONFIG_REGULATOR_MAX77686=y
CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_S2MPS11=y
@@ -324,18 +364,32 @@ CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_VEXPRESS=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MEDIA_USB_SUPPORT=y
CONFIG_USB_VIDEO_CLASS=y
CONFIG_USB_GSPCA=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=m
CONFIG_SOC_CAMERA_PLATFORM=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_RENESAS_VSP1=m
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ADV7180=m
CONFIG_DRM=y
CONFIG_DRM_RCAR_DU=m
CONFIG_DRM_TEGRA=y
CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_FB_ARMCLCD=y
CONFIG_FB_WM8505=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SIMPLE=y
CONFIG_FB_SH_MOBILE_MERAM=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_SOUND=y
@@ -343,6 +397,8 @@ CONFIG_SND=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_SH4_FSI=m
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_TEGRA=y
CONFIG_SND_SOC_TEGRA_RT5640=y
CONFIG_SND_SOC_TEGRA_WM8753=y
@@ -350,6 +406,8 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
CONFIG_SND_SOC_TEGRA_ALC5632=y
CONFIG_SND_SOC_TEGRA_MAX98090=y
CONFIG_SND_SOC_AK4642=m
CONFIG_SND_SOC_WM8978=m
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
@@ -362,6 +420,8 @@ CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_STI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_R8A66597_HCD=m
CONFIG_USB_RENESAS_USBHS=m
CONFIG_USB_STORAGE=y
CONFIG_USB_DWC3=y
CONFIG_USB_CHIPIDEA=y
@@ -374,6 +434,10 @@ CONFIG_SAMSUNG_USB3PHY=y
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y
CONFIG_USB_MXS_PHY=y
CONFIG_USB_RCAR_PHY=m
CONFIG_USB_RCAR_GEN2_PHY=m
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_ARMMMCI=y
@@ -392,12 +456,14 @@ CONFIG_MMC_SDHCI_ST=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_MVSDIO=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_IDMAC=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_EXYNOS=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_MMC_SUNXI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
@@ -421,10 +487,12 @@ CONFIG_RTC_DRV_AS3722=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_MAX8907=y
CONFIG_RTC_DRV_MAX77686=y
CONFIG_RTC_DRV_RS5C372=m
CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_TWL4030=y
CONFIG_RTC_DRV_TPS6586X=y
CONFIG_RTC_DRV_TPS65910=y
CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_EM3027=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_VT8500=y
@@ -436,6 +504,9 @@ CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_MV_XOR=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_SH_DMAE=y
CONFIG_RCAR_AUDMAC_PP=m
CONFIG_RCAR_DMAC=y
CONFIG_STE_DMA40=y
CONFIG_SIRF_DMA=y
CONFIG_TI_EDMA=y
@@ -468,6 +539,7 @@ CONFIG_IIO=y
CONFIG_XILINX_XADC=y
CONFIG_AK8975=y
CONFIG_PWM=y
CONFIG_PWM_RENESAS_TPU=y
CONFIG_PWM_TEGRA=y
CONFIG_PWM_VT8500=y
CONFIG_PHY_HIX5HD2_SATA=y

4
arch/arm/configs/omap2plus_defconfig
View File

@@ -114,6 +114,7 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC_BCH=y
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_OMAP2=y
@@ -248,6 +249,7 @@ CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_PBIAS=y
CONFIG_REGULATOR_TI_ABB=y
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y
CONFIG_REGULATOR_TPS65217=y
@@ -374,7 +376,7 @@ CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
CONFIG_OMAP_USB2=m
CONFIG_TI_PIPE3=m
CONFIG_TI_PIPE3=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set

96
arch/arm/include/asm/uaccess.h
View File

@@ -73,7 +73,7 @@ static inline void set_fs(mm_segment_t fs)
modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);
}
#define segment_eq(a,b) ((a) == (b))
#define segment_eq(a, b) ((a) == (b))
#define __addr_ok(addr) ({ \
unsigned long flag; \
@@ -84,7 +84,7 @@ static inline void set_fs(mm_segment_t fs)
(flag == 0); })
/* We use 33-bit arithmetic here... */
#define __range_ok(addr,size) ({ \
#define __range_ok(addr, size) ({ \
unsigned long flag, roksum; \
__chk_user_ptr(addr); \
__asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
@@ -123,7 +123,7 @@ extern int __get_user_64t_4(void *);
#define __GUP_CLOBBER_32t_8 "lr", "cc"
#define __GUP_CLOBBER_8 "lr", "cc"
#define __get_user_x(__r2,__p,__e,__l,__s) \
#define __get_user_x(__r2, __p, __e, __l, __s) \
__asm__ __volatile__ ( \
__asmeq("%0", "r0") __asmeq("%1", "r2") \
__asmeq("%3", "r1") \
@@ -134,7 +134,7 @@ extern int __get_user_64t_4(void *);
/* narrowing a double-word get into a single 32bit word register: */
#ifdef __ARMEB__
#define __get_user_x_32t(__r2, __p, __e, __l, __s) \
#define __get_user_x_32t(__r2, __p, __e, __l, __s) \
__get_user_x(__r2, __p, __e, __l, 32t_8)
#else
#define __get_user_x_32t __get_user_x
@@ -158,7 +158,7 @@ extern int __get_user_64t_4(void *);
#endif
#define __get_user_check(x,p) \
#define __get_user_check(x, p) \
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
register const typeof(*(p)) __user *__p asm("r0") = (p);\
@@ -196,10 +196,10 @@ extern int __get_user_64t_4(void *);
__e; \
})
#define get_user(x,p) \
#define get_user(x, p) \
({ \
might_fault(); \
__get_user_check(x,p); \
__get_user_check(x, p); \
})
extern int __put_user_1(void *, unsigned int);
@@ -207,7 +207,7 @@ extern int __put_user_2(void *, unsigned int);
extern int __put_user_4(void *, unsigned int);
extern int __put_user_8(void *, unsigned long long);
#define __put_user_x(__r2,__p,__e,__l,__s) \
#define __put_user_x(__r2, __p, __e, __l, __s) \
__asm__ __volatile__ ( \
__asmeq("%0", "r0") __asmeq("%2", "r2") \
__asmeq("%3", "r1") \
@@ -216,7 +216,7 @@ extern int __put_user_8(void *, unsigned long long);
: "0" (__p), "r" (__r2), "r" (__l) \
: "ip", "lr", "cc")
#define __put_user_check(x,p) \
#define __put_user_check(x, p) \
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
const typeof(*(p)) __user *__tmp_p = (p); \
@@ -242,10 +242,10 @@ extern int __put_user_8(void *, unsigned long long);
__e; \
})
#define put_user(x,p) \
#define put_user(x, p) \
({ \
might_fault(); \
__put_user_check(x,p); \
__put_user_check(x, p); \
})
#else /* CONFIG_MMU */
@@ -255,21 +255,21 @@ extern int __put_user_8(void *, unsigned long long);
*/
#define USER_DS KERNEL_DS
#define segment_eq(a,b) (1)
#define __addr_ok(addr) ((void)(addr),1)
#define __range_ok(addr,size) ((void)(addr),0)
#define segment_eq(a, b) (1)
#define __addr_ok(addr) ((void)(addr), 1)
#define __range_ok(addr, size) ((void)(addr), 0)
#define get_fs() (KERNEL_DS)
static inline void set_fs(mm_segment_t fs)
{
}
#define get_user(x,p) __get_user(x,p)
#define put_user(x,p) __put_user(x,p)
#define get_user(x, p) __get_user(x, p)
#define put_user(x, p) __put_user(x, p)
#endif /* CONFIG_MMU */
#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
#define access_ok(type, addr, size) (__range_ok(addr, size) == 0)
#define user_addr_max() \
(segment_eq(get_fs(), KERNEL_DS) ? ~0UL : get_fs())
@@ -283,35 +283,35 @@ static inline void set_fs(mm_segment_t fs)
* error occurs, and leave it unchanged on success. Note that these
* versions are void (ie, don't return a value as such).
*/
#define __get_user(x,ptr) \
#define __get_user(x, ptr) \
({ \
long __gu_err = 0; \
__get_user_err((x),(ptr),__gu_err); \
__get_user_err((x), (ptr), __gu_err); \
__gu_err; \
})
#define __get_user_error(x,ptr,err) \
#define __get_user_error(x, ptr, err) \
({ \
__get_user_err((x),(ptr),err); \
__get_user_err((x), (ptr), err); \
(void) 0; \
})
#define __get_user_err(x,ptr,err) \
#define __get_user_err(x, ptr, err) \
do { \
unsigned long __gu_addr = (unsigned long)(ptr); \
unsigned long __gu_val; \
__chk_user_ptr(ptr); \
might_fault(); \
switch (sizeof(*(ptr))) { \
case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \
case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \
case 4: __get_user_asm_word(__gu_val,__gu_addr,err); break; \
case 1: __get_user_asm_byte(__gu_val, __gu_addr, err); break; \
case 2: __get_user_asm_half(__gu_val, __gu_addr, err); break; \
case 4: __get_user_asm_word(__gu_val, __gu_addr, err); break; \
default: (__gu_val) = __get_user_bad(); \
} \
(x) = (__typeof__(*(ptr)))__gu_val; \
} while (0)
#define __get_user_asm_byte(x,addr,err) \
#define __get_user_asm_byte(x, addr, err) \
__asm__ __volatile__( \
"1: " TUSER(ldrb) " %1,[%2],#0\n" \
"2:\n" \
@@ -330,7 +330,7 @@ do { \
: "cc")
#ifndef __ARMEB__
#define __get_user_asm_half(x,__gu_addr,err) \
#define __get_user_asm_half(x, __gu_addr, err) \
({ \
unsigned long __b1, __b2; \
__get_user_asm_byte(__b1, __gu_addr, err); \
@@ -338,7 +338,7 @@ do { \
(x) = __b1 | (__b2 << 8); \
})
#else
#define __get_user_asm_half(x,__gu_addr,err) \
#define __get_user_asm_half(x, __gu_addr, err) \
({ \
unsigned long __b1, __b2; \
__get_user_asm_byte(__b1, __gu_addr, err); \
@@ -347,7 +347,7 @@ do { \
})
#endif
#define __get_user_asm_word(x,addr,err) \
#define __get_user_asm_word(x, addr, err) \
__asm__ __volatile__( \
"1: " TUSER(ldr) " %1,[%2],#0\n" \
"2:\n" \
@@ -365,35 +365,35 @@ do { \
: "r" (addr), "i" (-EFAULT) \
: "cc")
#define __put_user(x,ptr) \
#define __put_user(x, ptr) \
({ \
long __pu_err = 0; \
__put_user_err((x),(ptr),__pu_err); \
__put_user_err((x), (ptr), __pu_err); \
__pu_err; \
})
#define __put_user_error(x,ptr,err) \
#define __put_user_error(x, ptr, err) \
({ \
__put_user_err((x),(ptr),err); \
__put_user_err((x), (ptr), err); \
(void) 0; \
})
#define __put_user_err(x,ptr,err) \
#define __put_user_err(x, ptr, err) \
do { \
unsigned long __pu_addr = (unsigned long)(ptr); \
__typeof__(*(ptr)) __pu_val = (x); \
__chk_user_ptr(ptr); \
might_fault(); \
switch (sizeof(*(ptr))) { \
case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \
case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \
case 4: __put_user_asm_word(__pu_val,__pu_addr,err); break; \
case 8: __put_user_asm_dword(__pu_val,__pu_addr,err); break; \
case 1: __put_user_asm_byte(__pu_val, __pu_addr, err); break; \
case 2: __put_user_asm_half(__pu_val, __pu_addr, err); break; \
case 4: __put_user_asm_word(__pu_val, __pu_addr, err); break; \
case 8: __put_user_asm_dword(__pu_val, __pu_addr, err); break; \
default: __put_user_bad(); \
} \
} while (0)
#define __put_user_asm_byte(x,__pu_addr,err) \
#define __put_user_asm_byte(x, __pu_addr, err) \
__asm__ __volatile__( \
"1: " TUSER(strb) " %1,[%2],#0\n" \
"2:\n" \
@@ -411,22 +411,22 @@ do { \
: "cc")
#ifndef __ARMEB__
#define __put_user_asm_half(x,__pu_addr,err) \
#define __put_user_asm_half(x, __pu_addr, err) \
({ \
unsigned long __temp = (unsigned long)(x); \
unsigned long __temp = (__force unsigned long)(x); \
__put_user_asm_byte(__temp, __pu_addr, err); \
__put_user_asm_byte(__temp >> 8, __pu_addr + 1, err); \
})
#else
#define __put_user_asm_half(x,__pu_addr,err) \
#define __put_user_asm_half(x, __pu_addr, err) \
({ \
unsigned long __temp = (unsigned long)(x); \
unsigned long __temp = (__force unsigned long)(x); \
__put_user_asm_byte(__temp >> 8, __pu_addr, err); \
__put_user_asm_byte(__temp, __pu_addr + 1, err); \
})
#endif
#define __put_user_asm_word(x,__pu_addr,err) \
#define __put_user_asm_word(x, __pu_addr, err) \
__asm__ __volatile__( \
"1: " TUSER(str) " %1,[%2],#0\n" \
"2:\n" \
@@ -451,7 +451,7 @@ do { \
#define __reg_oper1 "%R2"
#endif
#define __put_user_asm_dword(x,__pu_addr,err) \
#define __put_user_asm_dword(x, __pu_addr, err) \
__asm__ __volatile__( \
ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \
ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \
@@ -480,9 +480,9 @@ extern unsigned long __must_check __copy_to_user_std(void __user *to, const void
extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned long n);
#else
#define __copy_from_user(to,from,n) (memcpy(to, (void __force *)from, n), 0)
#define __copy_to_user(to,from,n) (memcpy((void __force *)to, from, n), 0)
#define __clear_user(addr,n) (memset((void __force *)addr, 0, n), 0)
#define __copy_from_user(to, from, n) (memcpy(to, (void __force *)from, n), 0)
#define __copy_to_user(to, from, n) (memcpy((void __force *)to, from, n), 0)
#define __clear_user(addr, n) (memset((void __force *)addr, 0, n), 0)
#endif
static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)

2
arch/arm/kernel/perf_event_cpu.c
View File

@@ -231,7 +231,7 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
/*
* PMU platform driver and devicetree bindings.
*/
static struct of_device_id cpu_pmu_of_device_ids[] = {
static const struct of_device_id cpu_pmu_of_device_ids[] = {
{.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init},
{.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
{.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init},

2
arch/arm/mach-asm9260/Kconfig
View File

@@ -2,5 +2,7 @@ config MACH_ASM9260
bool "Alphascale ASM9260"
depends on ARCH_MULTI_V5
select CPU_ARM926T
select ASM9260_TIMER
select GENERIC_CLOCKEVENTS
help
Support for Alphascale ASM9260 based platform.

1
arch/arm/mach-at91/Kconfig
View File

@@ -64,7 +64,6 @@ config SOC_SAMA5D4
select SOC_SAMA5
select CLKSRC_MMIO
select CACHE_L2X0
select CACHE_PL310
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
select HAVE_AT91_SMD

2
arch/arm/mach-at91/at91rm9200_time.c
View File

@@ -183,7 +183,7 @@ static struct clock_event_device clkevt = {
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
static struct of_device_id at91rm9200_st_timer_ids[] = {
static const struct of_device_id at91rm9200_st_timer_ids[] = {
{ .compatible = "atmel,at91rm9200-st" },
{ /* sentinel */ }
};

8
arch/arm/mach-at91/generic.h
View File

@@ -35,10 +35,10 @@ extern void __init at91sam9260_pm_init(void);
extern void __init at91sam9g45_pm_init(void);
extern void __init at91sam9x5_pm_init(void);
#else
void __init at91rm9200_pm_init(void) { }
void __init at91sam9260_pm_init(void) { }
void __init at91sam9g45_pm_init(void) { }
void __init at91sam9x5_pm_init(void) { }
static inline void __init at91rm9200_pm_init(void) { }
static inline void __init at91sam9260_pm_init(void) { }
static inline void __init at91sam9g45_pm_init(void) { }
static inline void __init at91sam9x5_pm_init(void) { }
#endif
#endif /* _AT91_GENERIC_H */

4
arch/arm/mach-at91/pm.c
View File

@@ -226,7 +226,7 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
static struct of_device_id ramc_ids[] = {
static const struct of_device_id ramc_ids[] __initconst = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
@@ -234,7 +234,7 @@ static struct of_device_id ramc_ids[] = {
{ /*sentinel*/ }
};
static void at91_dt_ramc(void)
static __init void at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;

2
arch/arm/mach-axxia/axxia.c
View File

@@ -16,7 +16,7 @@
#include <linux/init.h>
#include <asm/mach/arch.h>
static const char *axxia_dt_match[] __initconst = {
static const char *const axxia_dt_match[] __initconst = {
"lsi,axm5516",
"lsi,axm5516-sim",
"lsi,axm5516-emu",

4
arch/arm/mach-bcm/Kconfig
View File

@@ -68,7 +68,7 @@ config ARCH_BCM_MOBILE
This enables support for systems based on Broadcom mobile SoCs.
config ARCH_BCM_281XX
bool "Broadcom BCM281XX SoC family"
bool "Broadcom BCM281XX SoC family" if ARCH_MULTI_V7
select ARCH_BCM_MOBILE
select HAVE_SMP
help
@@ -77,7 +77,7 @@ config ARCH_BCM_281XX
variants.
config ARCH_BCM_21664
bool "Broadcom BCM21664 SoC family"
bool "Broadcom BCM21664 SoC family" if ARCH_MULTI_V7
select ARCH_BCM_MOBILE
select HAVE_SMP
help

2
arch/arm/mach-bcm/brcmstb.c
View File

@@ -17,7 +17,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static const char *brcmstb_match[] __initconst = {
static const char *const brcmstb_match[] __initconst = {
"brcm,bcm7445",
"brcm,brcmstb",
NULL

2
arch/arm/mach-davinci/Kconfig
View File

@@ -32,12 +32,14 @@ config ARCH_DAVINCI_DM646x
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137/AM17x based system"
depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
select ARCH_DAVINCI_DA8XX
select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
select CP_INTC
config ARCH_DAVINCI_DA850
bool "DA850/OMAP-L138/AM18x based system"
depends on !ARCH_DAVINCI_DMx || AUTO_ZRELADDR
select ARCH_DAVINCI_DA8XX
select CP_INTC

2
arch/arm/mach-davinci/da8xx-dt.c
View File

@@ -20,7 +20,7 @@
#define DA8XX_NUM_UARTS 3
static struct of_device_id da8xx_irq_match[] __initdata = {
static const struct of_device_id da8xx_irq_match[] __initconst = {
{ .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
{ }
};

4
arch/arm/mach-davinci/mux.c
View File

@@ -30,7 +30,7 @@ static void __iomem *pinmux_base;
/*
* Sets the DAVINCI MUX register based on the table
*/
int __init_or_module davinci_cfg_reg(const unsigned long index)
int davinci_cfg_reg(const unsigned long index)
{
static DEFINE_SPINLOCK(mux_spin_lock);
struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -101,7 +101,7 @@ int __init_or_module davinci_cfg_reg(const unsigned long index)
}
EXPORT_SYMBOL(davinci_cfg_reg);
int __init_or_module davinci_cfg_reg_list(const short pins[])
int davinci_cfg_reg_list(const short pins[])
{
int i, error = -EINVAL;

2
arch/arm/mach-exynos/exynos.c
View File

@@ -227,7 +227,7 @@ static void __init exynos_dt_machine_init(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos_dt_compat[] __initconst = {
static char const *const exynos_dt_compat[] __initconst = {
"samsung,exynos3",
"samsung,exynos3250",
"samsung,exynos4",

2
arch/arm/mach-exynos/suspend.c
View File

@@ -587,7 +587,7 @@ static struct exynos_pm_data exynos5420_pm_data = {
.cpu_suspend = exynos5420_cpu_suspend,
};
static struct of_device_id exynos_pmu_of_device_ids[] = {
static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
{
.compatible = "samsung,exynos3250-pmu",
.data = &exynos3250_pm_data,

2
arch/arm/mach-highbank/highbank.c
View File

@@ -169,7 +169,7 @@ static void __init highbank_init(void)
platform_device_register(&highbank_cpuidle_device);
}
static const char *highbank_match[] __initconst = {
static const char *const highbank_match[] __initconst = {
"calxeda,highbank",
"calxeda,ecx-2000",
NULL,

8
arch/arm/mach-hisi/hisilicon.c
View File

@@ -45,7 +45,7 @@ static void __init hi3620_map_io(void)
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static const char *hi3xxx_compat[] __initconst = {
static const char *const hi3xxx_compat[] __initconst = {
"hisilicon,hi3620-hi4511",
NULL,
};
@@ -55,7 +55,7 @@ DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.dt_compat = hi3xxx_compat,
MACHINE_END
static const char *hix5hd2_compat[] __initconst = {
static const char *const hix5hd2_compat[] __initconst = {
"hisilicon,hix5hd2",
NULL,
};
@@ -64,7 +64,7 @@ DT_MACHINE_START(HIX5HD2_DT, "Hisilicon HIX5HD2 (Flattened Device Tree)")
.dt_compat = hix5hd2_compat,
MACHINE_END
static const char *hip04_compat[] __initconst = {
static const char *const hip04_compat[] __initconst = {
"hisilicon,hip04-d01",
NULL,
};
@@ -73,7 +73,7 @@ DT_MACHINE_START(HIP04, "Hisilicon HiP04 (Flattened Device Tree)")
.dt_compat = hip04_compat,
MACHINE_END
static const char *hip01_compat[] __initconst = {
static const char *const hip01_compat[] __initconst = {
"hisilicon,hip01",
"hisilicon,hip01-ca9x2",
NULL,

2
arch/arm/mach-imx/mmdc.c
View File

@@ -68,7 +68,7 @@ int imx_mmdc_get_ddr_type(void)
return ddr_type;
}
static struct of_device_id imx_mmdc_dt_ids[] = {
static const struct of_device_id imx_mmdc_dt_ids[] = {
{ .compatible = "fsl,imx6q-mmdc", },
{ /* sentinel */ }
};

19
arch/arm/mach-ixp4xx/include/mach/io.h
View File

@@ -245,8 +245,10 @@ static inline void outb(u8 value, u32 addr)
}
#define outsb outsb
static inline void outsb(u32 io_addr, const u8 *vaddr, u32 count)
static inline void outsb(u32 io_addr, const void *p, u32 count)
{
const u8 *vaddr = p;
while (count--)
outb(*vaddr++, io_addr);
}
@@ -262,8 +264,9 @@ static inline void outw(u16 value, u32 addr)
}
#define outsw outsw
static inline void outsw(u32 io_addr, const u16 *vaddr, u32 count)
static inline void outsw(u32 io_addr, const void *p, u32 count)
{
const u16 *vaddr = p;
while (count--)
outw(cpu_to_le16(*vaddr++), io_addr);
}
@@ -275,8 +278,9 @@ static inline void outl(u32 value, u32 addr)
}
#define outsl outsl
static inline void outsl(u32 io_addr, const u32 *vaddr, u32 count)
static inline void outsl(u32 io_addr, const void *p, u32 count)
{
const u32 *vaddr = p;
while (count--)
outl(cpu_to_le32(*vaddr++), io_addr);
}
@@ -294,8 +298,9 @@ static inline u8 inb(u32 addr)
}
#define insb insb
static inline void insb(u32 io_addr, u8 *vaddr, u32 count)
static inline void insb(u32 io_addr, void *p, u32 count)
{
u8 *vaddr = p;
while (count--)
*vaddr++ = inb(io_addr);
}
@@ -313,8 +318,9 @@ static inline u16 inw(u32 addr)
}
#define insw insw
static inline void insw(u32 io_addr, u16 *vaddr, u32 count)
static inline void insw(u32 io_addr, void *p, u32 count)
{
u16 *vaddr = p;
while (count--)
*vaddr++ = le16_to_cpu(inw(io_addr));
}
@@ -330,8 +336,9 @@ static inline u32 inl(u32 addr)
}
#define insl insl
static inline void insl(u32 io_addr, u32 *vaddr, u32 count)
static inline void insl(u32 io_addr, void *p, u32 count)
{
u32 *vaddr = p;
while (count--)
*vaddr++ = le32_to_cpu(inl(io_addr));
}

2
arch/arm/mach-keystone/keystone.c
View File

@@ -103,7 +103,7 @@ static void __init keystone_init_meminfo(void)
pr_info("Switching to high address space at 0x%llx\n", (u64)offset);
}
static const char *keystone_match[] __initconst = {
static const char *const keystone_match[] __initconst = {
"ti,keystone",
NULL,
};

2
arch/arm/mach-keystone/pm_domain.c
View File

@@ -61,7 +61,7 @@ static struct pm_clk_notifier_block platform_domain_notifier = {
.pm_domain = &keystone_pm_domain,
};
static struct of_device_id of_keystone_table[] = {
static const struct of_device_id of_keystone_table[] = {
{.compatible = "ti,keystone"},
{ /* end of list */ },
};

2
arch/arm/mach-mmp/time.c
View File

@@ -213,7 +213,7 @@ void __init timer_init(int irq)
}
#ifdef CONFIG_OF
static struct of_device_id mmp_timer_dt_ids[] = {
static const struct of_device_id mmp_timer_dt_ids[] = {
{ .compatible = "mrvl,mmp-timer", },
{}
};

8
arch/arm/mach-msm/board-halibut.c
View File

@@ -20,6 +20,7 @@
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@@ -46,15 +47,20 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = MSM_GPIO_TO_INT(49),
.end = MSM_GPIO_TO_INT(49),
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev.platform_data = &smc91x_platdata,
};
static struct platform_device *devices[] __initdata = {

8
arch/arm/mach-msm/board-qsd8x50.c
View File

@@ -22,6 +22,7 @@
#include <linux/usb/msm_hsusb.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -49,15 +50,20 @@ static struct resource smc91x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev.platform_data = &smc91x_platdata,
};
static int __init msm_init_smc91x(void)

2
arch/arm/mach-mvebu/coherency.c
View File

@@ -51,7 +51,7 @@ enum {
COHERENCY_FABRIC_TYPE_ARMADA_380,
};
static struct of_device_id of_coherency_table[] = {
static const struct of_device_id of_coherency_table[] = {
{.compatible = "marvell,coherency-fabric",
.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
{.compatible = "marvell,armada-375-coherency-fabric",

2
arch/arm/mach-mvebu/pmsu.c
View File

@@ -104,7 +104,7 @@ static void __iomem *pmsu_mp_base;
static void *mvebu_cpu_resume;
static struct of_device_id of_pmsu_table[] = {
static const struct of_device_id of_pmsu_table[] = {
{ .compatible = "marvell,armada-370-pmsu", },
{ .compatible = "marvell,armada-370-xp-pmsu", },
{ .compatible = "marvell,armada-380-pmsu", },

2
arch/arm/mach-mvebu/system-controller.c
View File

@@ -126,7 +126,7 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
return -ENODEV;
}
#ifdef CONFIG_SMP
#if defined(CONFIG_SMP) && defined(CONFIG_MACH_MVEBU_V7)
void mvebu_armada375_smp_wa_init(void)
{
u32 dev, rev;

2
arch/arm/mach-nspire/nspire.c
View File

@@ -27,7 +27,7 @@
#include "mmio.h"
#include "clcd.h"
static const char *nspire_dt_match[] __initconst = {
static const char *const nspire_dt_match[] __initconst = {
"ti,nspire",
"ti,nspire-cx",
"ti,nspire-tp",

2
arch/arm/mach-omap2/Makefile
View File

@@ -190,7 +190,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o

3688
arch/arm/mach-omap2/cclock3xxx_data.c
View File

File diff suppressed because it is too large Load Diff

16
arch/arm/mach-omap2/clock.c
View File

@@ -23,7 +23,6 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clk-private.h>
#include <asm/cpu.h>
#include <trace/events/power.h>
@@ -632,21 +631,6 @@ const struct clk_hw_omap_ops clkhwops_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap_clocks_register - register an array of omap_clk
* @ocs: pointer to an array of omap_clk to register
*/
void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
{
struct omap_clk *c;
for (c = oclks; c < oclks + cnt; c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
/**
* omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
* @mpurate_ck_name: clk name of the clock to change rate

14
arch/arm/mach-omap2/clock.h
View File

@@ -40,23 +40,29 @@ struct omap_clk {
struct clockdomain;
#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
static struct clk _name = { \
static struct clk_core _name##_core = { \
.name = #_name, \
.hw = &_name##_hw.hw, \
.parent_names = _parent_array_name, \
.num_parents = ARRAY_SIZE(_parent_array_name), \
.ops = &_clkops_name, \
}; \
static struct clk _name = { \
.core = &_name##_core, \
};
#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
_clkops_name, _flags) \
static struct clk _name = { \
static struct clk_core _name##_core = { \
.name = #_name, \
.hw = &_name##_hw.hw, \
.parent_names = _parent_array_name, \
.num_parents = ARRAY_SIZE(_parent_array_name), \
.ops = &_clkops_name, \
.flags = _flags, \
}; \
static struct clk _name = { \
.core = &_name##_core, \
};
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
@@ -238,7 +244,6 @@ struct ti_clk_features {
extern struct ti_clk_features ti_clk_features;
extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_dummy;
extern const struct clkops clkops_omap2_dflt;
extern struct clk_functions omap2_clk_functions;
@@ -247,7 +252,6 @@ extern const struct clksel_rate gpt_32k_rates[];
extern const struct clksel_rate gpt_sys_rates[];
extern const struct clksel_rate gfx_l3_rates[];
extern const struct clksel_rate dsp_ick_rates[];
extern struct clk dummy_ck;
extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
extern const struct clk_hw_omap_ops clkhwops_wait;
@@ -272,7 +276,5 @@ extern void __iomem *clk_memmaps[];
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
void __init ti_clk_init_features(void);
#endif

11
arch/arm/mach-omap2/clock_common_data.c
View File

@@ -16,7 +16,6 @@
* OMAP3xxx clock definition files.
*/
#include <linux/clk-private.h>
#include "clock.h"
/* clksel_rate data common to 24xx/343x */
@@ -114,13 +113,3 @@ const struct clksel_rate div31_1to31_rates[] = {
{ .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
{ .div = 0 },
};
/* Clocks shared between various OMAP SoCs */
static struct clk_ops dummy_ck_ops = {};
struct clk dummy_ck = {
.name = "dummy_clk",
.ops = &dummy_ck_ops,
.flags = CLK_IS_BASIC,
};

13
arch/arm/mach-omap2/dpll3xxx.c
View File

@@ -410,7 +410,7 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
int r;
struct dpll_data *dd;
struct clk *parent;
struct clk_hw *parent;
dd = clk->dpll_data;
if (!dd)
@@ -427,13 +427,13 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
}
}
parent = __clk_get_parent(hw->clk);
parent = __clk_get_hw(__clk_get_parent(hw->clk));
if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
WARN_ON(parent != dd->clk_bypass);
WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
r = _omap3_noncore_dpll_bypass(clk);
} else {
WARN_ON(parent != dd->clk_ref);
WARN_ON(parent != __clk_get_hw(dd->clk_ref));
r = _omap3_noncore_dpll_lock(clk);
}
@@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
* in failure.
*/
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk)
{
@@ -549,7 +551,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (!dd)
return -EINVAL;
if (__clk_get_parent(hw->clk) != dd->clk_ref)
if (__clk_get_hw(__clk_get_parent(hw->clk)) !=
__clk_get_hw(dd->clk_ref))
return -EINVAL;
if (dd->last_rounded_rate == 0)

2
arch/arm/mach-omap2/dpll44xx.c
View File

@@ -202,6 +202,8 @@ out:
* in failure.
*/
long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
unsigned long *best_parent_rate,
struct clk_hw **best_parent_clk)
{

26
arch/arm/mach-omap2/io.c
View File

@@ -461,7 +461,17 @@ void __init omap3_init_early(void)
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap3xxx_clk_init;
if (!of_have_populated_dt()) {
omap3_prcm_legacy_iomaps_init();
if (soc_is_am35xx())
omap_clk_soc_init = am35xx_clk_legacy_init;
else if (cpu_is_omap3630())
omap_clk_soc_init = omap36xx_clk_legacy_init;
else if (omap_rev() == OMAP3430_REV_ES1_0)
omap_clk_soc_init = omap3430es1_clk_legacy_init;
else
omap_clk_soc_init = omap3430_clk_legacy_init;
}
}
void __init omap3430_init_early(void)
@@ -753,15 +763,17 @@ int __init omap_clk_init(void)
ti_clk_init_features();
ret = of_prcm_init();
if (ret)
return ret;
if (of_have_populated_dt()) {
ret = of_prcm_init();
if (ret)
return ret;
of_clk_init(NULL);
of_clk_init(NULL);
ti_dt_clk_init_retry_clks();
ti_dt_clk_init_retry_clks();
ti_dt_clockdomains_setup();
ti_dt_clockdomains_setup();
}
ret = omap_clk_soc_init();

2
arch/arm/mach-omap2/omap4-common.c
View File

@@ -242,7 +242,7 @@ static int __init omap4_sar_ram_init(void)
}
omap_early_initcall(omap4_sar_ram_init);
static struct of_device_id gic_match[] = {
static const struct of_device_id gic_match[] = {
{ .compatible = "arm,cortex-a9-gic", },
{ .compatible = "arm,cortex-a15-gic", },
{ },

1
arch/arm/mach-omap2/prm.h
View File

@@ -20,6 +20,7 @@ extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int of_prcm_init(void);
void omap3_prcm_legacy_iomaps_init(void);
# endif
/*

2
arch/arm/mach-omap2/prm3xxx.c
View File

@@ -674,7 +674,7 @@ int __init omap3xxx_prm_init(void)
return prm_register(&omap3xxx_prm_ll_data);
}
static struct of_device_id omap3_prm_dt_match_table[] = {
static const struct of_device_id omap3_prm_dt_match_table[] = {
{ .compatible = "ti,omap3-prm" },
{ }
};

2
arch/arm/mach-omap2/prm44xx.c
View File

@@ -712,7 +712,7 @@ int __init omap44xx_prm_init(void)
return prm_register(&omap44xx_prm_ll_data);
}
static struct of_device_id omap_prm_dt_match_table[] = {
static const struct of_device_id omap_prm_dt_match_table[] = {
{ .compatible = "ti,omap4-prm" },
{ .compatible = "ti,omap5-prm" },
{ .compatible = "ti,dra7-prm" },

11
arch/arm/mach-omap2/prm_common.c
View File

@@ -35,6 +35,8 @@
#include "prm44xx.h"
#include "common.h"
#include "clock.h"
#include "cm.h"
#include "control.h"
/*
* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -641,6 +643,15 @@ int __init of_prcm_init(void)
return 0;
}
void __init omap3_prcm_legacy_iomaps_init(void)
{
ti_clk_ll_ops = &omap_clk_ll_ops;
clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
}
static int __init prm_late_init(void)
{
if (prm_ll_data->late_init)

1
arch/arm/mach-prima2/Kconfig
View File

@@ -27,7 +27,6 @@ config ARCH_ATLAS7
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_SMP
select SMP_ON_UP if SMP
help
Support for CSR SiRFSoC ARM Cortex A7 Platform

6
arch/arm/mach-prima2/common.c
View File

@@ -21,7 +21,7 @@ static void __init sirfsoc_init_late(void)
}
#ifdef CONFIG_ARCH_ATLAS6
static const char *atlas6_dt_match[] __initconst = {
static const char *const atlas6_dt_match[] __initconst = {
"sirf,atlas6",
NULL
};
@@ -36,7 +36,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_PRIMA2
static const char *prima2_dt_match[] __initconst = {
static const char *const prima2_dt_match[] __initconst = {
"sirf,prima2",
NULL
};
@@ -52,7 +52,7 @@ MACHINE_END
#endif
#ifdef CONFIG_ARCH_ATLAS7
static const char *atlas7_dt_match[] __initdata = {
static const char *const atlas7_dt_match[] __initconst = {
"sirf,atlas7",
NULL
};

2
arch/arm/mach-prima2/platsmp.c
View File

@@ -40,7 +40,7 @@ static void sirfsoc_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static struct of_device_id clk_ids[] = {
static const struct of_device_id clk_ids[] = {
{ .compatible = "sirf,atlas7-clkc" },
{},
};

5
arch/arm/mach-pxa/idp.c
View File

@@ -81,11 +81,16 @@ static struct resource smc91x_resources[] = {
}
};
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_32BIT | SMC91X_USE_DMA | SMC91X_NOWAIT,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev.platform_data = &smc91x_platdata,
};
static void idp_backlight_power(int on)

8
arch/arm/mach-pxa/lpd270.c
View File

@@ -24,6 +24,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
#include <asm/types.h>
#include <asm/setup.h>
@@ -189,15 +190,20 @@ static struct resource smc91x_resources[] = {
[1] = {
.start = LPD270_ETHERNET_IRQ,
.end = LPD270_ETHERNET_IRQ,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT;
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev.platform_data = &smc91x_platdata,
};
static struct resource lpd270_flash_resources[] = {

7
arch/arm/mach-realview/core.c
View File

@@ -28,6 +28,7 @@
#include <linux/platform_data/video-clcd-versatile.h>
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/smc91x.h>
#include <linux/ata_platform.h>
#include <linux/amba/mmci.h>
#include <linux/gfp.h>
@@ -94,6 +95,10 @@ static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
};
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_32BIT | SMC91X_NOWAIT,
};
static struct platform_device realview_eth_device = {
.name = "smsc911x",
.id = 0,
@@ -107,6 +112,8 @@ int realview_eth_register(const char *name, struct resource *res)
realview_eth_device.resource = res;
if (strcmp(realview_eth_device.name, "smsc911x") == 0)
realview_eth_device.dev.platform_data = &smsc911x_config;
else
realview_eth_device.dev.platform_data = &smc91x_platdata;
return platform_device_register(&realview_eth_device);
}

2
arch/arm/mach-realview/realview_eb.c
View File

@@ -234,7 +234,7 @@ static struct resource realview_eb_eth_resources[] = {
[1] = {
.start = IRQ_EB_ETH,
.end = IRQ_EB_ETH,
.flags = IORESOURCE_IRQ,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};

1
arch/arm/mach-rockchip/Kconfig
View File

@@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select DW_APB_TIMER_OF
select REGULATOR if PM
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK

6
arch/arm/mach-rockchip/pm.h
View File

@@ -24,7 +24,13 @@ extern unsigned long rkpm_bootdata_ddr_data;
extern unsigned long rk3288_bootram_sz;
void rockchip_slp_cpu_resume(void);
#ifdef CONFIG_PM_SLEEP
void __init rockchip_suspend_init(void);
#else
static inline void rockchip_suspend_init(void)
{
}
#endif
/****** following is rk3288 defined **********/
#define RK3288_PMU_WAKEUP_CFG0 0x00

2
arch/arm/mach-s5pv210/s5pv210.c
View File

@@ -63,7 +63,7 @@ static void __init s5pv210_dt_init_late(void)
s5pv210_pm_init();
}
static char const *s5pv210_dt_compat[] __initconst = {
static char const *const s5pv210_dt_compat[] __initconst = {
"samsung,s5pc110",
"samsung,s5pv210",
NULL

6
arch/arm/mach-sa1100/neponset.c
View File

@@ -12,6 +12,7 @@
#include <linux/pm.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/smc91x.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
@@ -258,12 +259,17 @@ static int neponset_probe(struct platform_device *dev)
0x02000000, "smc91x-attrib"),
{ .flags = IORESOURCE_IRQ },
};
struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
};
struct platform_device_info smc91x_devinfo = {
.parent = &dev->dev,
.name = "smc91x",
.id = 0,
.res = smc91x_resources,
.num_res = ARRAY_SIZE(smc91x_resources),
.data = &smc91c_platdata,
.size_data = sizeof(smc91c_platdata),
};
int ret, irq;

7
arch/arm/mach-sa1100/pleb.c
View File

@@ -11,6 +11,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/mtd/partitions.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/setup.h>
@@ -43,12 +44,18 @@ static struct resource smc91x_resources[] = {
#endif
};
static struct smc91x_platdata smc91x_platdata = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
.dev = {
.platform_data = &smc91c_platdata,
},
};
static struct platform_device *devices[] __initdata = {

2
arch/arm/mach-shmobile/setup-emev2.c
View File

@@ -37,7 +37,7 @@ static void __init emev2_map_io(void)
iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
}
static const char *emev2_boards_compat_dt[] __initconst = {
static const char *const emev2_boards_compat_dt[] __initconst = {
"renesas,emev2",
NULL,
};

1
arch/arm/mach-sti/Kconfig
View File

@@ -13,6 +13,7 @@ menuconfig ARCH_STI
select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select RESET_CONTROLLER
help
Include support for STiH41x SOCs like STiH415/416 using the device tree
for discovery

2
arch/arm/mach-tegra/tegra.c
View File

@@ -91,8 +91,6 @@ static void __init tegra_dt_init(void)
struct soc_device *soc_dev;
struct device *parent = NULL;
tegra_clocks_apply_init_table();
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
if (!soc_dev_attr)
goto out;

2
arch/arm/mach-ux500/pm_domains.c
View File

@@ -49,7 +49,7 @@ static struct generic_pm_domain *ux500_pm_domains[NR_DOMAINS] = {
[DOMAIN_VAPE] = &ux500_pm_domain_vape,
};
static struct of_device_id ux500_pm_domain_matches[] = {
static const struct of_device_id ux500_pm_domain_matches[] __initconst = {
{ .compatible = "stericsson,ux500-pm-domains", },
{ },
};

2
arch/arm/mach-versatile/versatile_dt.c
View File

@@ -35,7 +35,7 @@ static void __init versatile_dt_init(void)
versatile_auxdata_lookup, NULL);
}
static const char *versatile_dt_match[] __initconst = {
static const char *const versatile_dt_match[] __initconst = {
"arm,versatile-ab",
"arm,versatile-pb",
NULL,

1
arch/arm/mach-vexpress/Kconfig
View File

@@ -73,6 +73,7 @@ config ARCH_VEXPRESS_TC2_PM
depends on MCPM
select ARM_CCI
select ARCH_VEXPRESS_SPC
select ARM_CPU_SUSPEND
help
Support for CPU and cluster power management on Versatile Express
with a TC2 (A15x2 A7x3) big.LITTLE core tile.

7
arch/arm/mm/Kconfig
View File

@@ -892,13 +892,6 @@ config CACHE_L2X0
if CACHE_L2X0
config CACHE_PL310
bool
default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
help
This option enables optimisations for the PL310 cache
controller.
config PL310_ERRATA_588369
bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
help

2
arch/arm/mm/dma-mapping.c
View File

@@ -1106,7 +1106,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
int i = 0;
if (array_size <= PAGE_SIZE)
pages = kzalloc(array_size, gfp);
pages = kzalloc(array_size, GFP_KERNEL);
else
pages = vzalloc(array_size);
if (!pages)

8
arch/arm64/boot/dts/arm/foundation-v8.dts
View File

@@ -34,6 +34,7 @@
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
@@ -41,6 +42,7 @@
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
@@ -48,6 +50,7 @@
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
@@ -55,6 +58,11 @@
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};

14
arch/arm64/boot/dts/arm/juno.dts
View File

@@ -39,6 +39,7 @@
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
};
A57_1: cpu@1 {
@@ -46,6 +47,7 @@
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A57_L2>;
};
A53_0: cpu@100 {
@@ -53,6 +55,7 @@
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_1: cpu@101 {
@@ -60,6 +63,7 @@
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_2: cpu@102 {
@@ -67,6 +71,7 @@
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_3: cpu@103 {
@@ -74,6 +79,15 @@
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A57_L2: l2-cache0 {
compatible = "cache";
};
A53_L2: l2-cache1 {
compatible = "cache";
};
};

8
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View File

@@ -37,6 +37,7 @@
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
@@ -44,6 +45,7 @@
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
device_type = "cpu";
@@ -51,6 +53,7 @@
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
device_type = "cpu";
@@ -58,6 +61,11 @@
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};

2
arch/arm64/crypto/Makefile
View File

@@ -29,7 +29,7 @@ aes-ce-blk-y := aes-glue-ce.o aes-ce.o
obj-$(CONFIG_CRYPTO_AES_ARM64_NEON_BLK) += aes-neon-blk.o
aes-neon-blk-y := aes-glue-neon.o aes-neon.o
AFLAGS_aes-ce.o := -DINTERLEAVE=2 -DINTERLEAVE_INLINE
AFLAGS_aes-ce.o := -DINTERLEAVE=4
AFLAGS_aes-neon.o := -DINTERLEAVE=4
CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS

5
arch/arm64/include/asm/assembler.h
View File

@@ -20,6 +20,9 @@
#error "Only include this from assembly code"
#endif
#ifndef __ASM_ASSEMBLER_H
#define __ASM_ASSEMBLER_H
#include <asm/ptrace.h>
#include <asm/thread_info.h>
@@ -155,3 +158,5 @@ lr .req x30 // link register
#endif
orr \rd, \lbits, \hbits, lsl #32
.endm
#endif /* __ASM_ASSEMBLER_H */

2
arch/arm64/include/asm/cpuidle.h
View File

@@ -1,6 +1,8 @@
#ifndef __ASM_CPUIDLE_H
#define __ASM_CPUIDLE_H
#include <asm/proc-fns.h>
#ifdef CONFIG_CPU_IDLE
extern int cpu_init_idle(unsigned int cpu);
extern int cpu_suspend(unsigned long arg);

6
arch/arm64/include/asm/insn.h
View File

@@ -264,8 +264,10 @@ __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000)
__AARCH64_INSN_FUNCS(cbnz, 0xFE000000, 0x35000000)
__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)

2
arch/arm64/include/asm/pgtable.h
View File

@@ -460,7 +460,7 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
return pte;
}

3
arch/arm64/include/asm/processor.h
View File

@@ -45,7 +45,8 @@
#define STACK_TOP STACK_TOP_MAX
#endif /* CONFIG_COMPAT */
#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK
extern phys_addr_t arm64_dma_phys_limit;
#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
#endif /* __KERNEL__ */
struct debug_info {

5
arch/arm64/include/asm/tlbflush.h
View File

@@ -24,11 +24,6 @@
#include <linux/sched.h>
#include <asm/cputype.h>
extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
extern struct cpu_tlb_fns cpu_tlb;
/*
* TLB Management
* ==============

4
arch/arm64/include/asm/uaccess.h
View File

@@ -63,7 +63,7 @@ static inline void set_fs(mm_segment_t fs)
current_thread_info()->addr_limit = fs;
}
#define segment_eq(a,b) ((a) == (b))
#define segment_eq(a, b) ((a) == (b))
/*
* Return 1 if addr < current->addr_limit, 0 otherwise.
@@ -147,7 +147,7 @@ do { \
default: \
BUILD_BUG(); \
} \
(x) = (__typeof__(*(ptr)))__gu_val; \
(x) = (__force __typeof__(*(ptr)))__gu_val; \
} while (0)
#define __get_user(x, ptr) \

5
arch/arm64/kernel/Makefile
View File

@@ -15,8 +15,9 @@ CFLAGS_REMOVE_return_address.o = -pg
arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
entry-fpsimd.o process.o ptrace.o setup.o signal.o \
sys.o stacktrace.o time.o traps.o io.o vdso.o \
hyp-stub.o psci.o cpu_ops.o insn.o return_address.o \
cpuinfo.o cpu_errata.o alternative.o cacheinfo.o
hyp-stub.o psci.o psci-call.o cpu_ops.o insn.o \
return_address.o cpuinfo.o cpu_errata.o \
alternative.o cacheinfo.o
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
sys_compat.o entry32.o \

2
arch/arm64/kernel/ftrace.c
View File

@@ -156,7 +156,7 @@ static int ftrace_modify_graph_caller(bool enable)
branch = aarch64_insn_gen_branch_imm(pc,
(unsigned long)ftrace_graph_caller,
AARCH64_INSN_BRANCH_LINK);
AARCH64_INSN_BRANCH_NOLINK);
nop = aarch64_insn_gen_nop();
if (enable)

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