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Merge branch 'remotes/lorenzo/pci/cadence'

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- Deprecate 'cdns,max-outbound-regions' and 'cdns,no-bar-match-nbits'
    bindings in favor of deriving them from 'ranges' and 'dma-ranges'
    (Kishon Vijay Abraham I)

  - Read Vendor and Device ID as 32 bits (not 16) from DT (Kishon Vijay
    Abraham I)

* remotes/lorenzo/pci/cadence:
  PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT
  PCI: cadence: Remove "cdns,max-outbound-regions" DT property
  dt-bindings: PCI: cadence: Deprecate inbound/outbound specific bindings
This commit is contained in:
Bjorn Helgaas
2020-06-04 12:59:15 -05:00
parent a1dcc1aa6f 7fb39bf2a1
commit 712879510f
7 changed files with 41 additions and 23 deletions
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10
drivers/pci/controller/cadence/pcie-cadence-host.c
View File

@@ -140,9 +140,6 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
for_each_of_pci_range(&parser, &range) {
bool is_io;
if (r >= rc->max_regions)
break;
if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
is_io = false;
else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
@@ -219,17 +216,14 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
pcie = &rc->pcie;
pcie->is_rc = true;
rc->max_regions = 32;
of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
rc->no_bar_nbits = 32;
of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
rc->vendor_id = 0xffff;
of_property_read_u16(np, "vendor-id", &rc->vendor_id);
of_property_read_u32(np, "vendor-id", &rc->vendor_id);
rc->device_id = 0xffff;
of_property_read_u16(np, "device-id", &rc->device_id);
of_property_read_u32(np, "device-id", &rc->device_id);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
pcie->reg_base = devm_ioremap_resource(dev, res);

6
drivers/pci/controller/cadence/pcie-cadence.h
View File

@@ -251,7 +251,6 @@ struct cdns_pcie {
* @bus_range: first/last buses behind the PCIe host controller
* @cfg_base: IO mapped window to access the PCI configuration space of a
* single function at a time
* @max_regions: maximum number of regions supported by the hardware
* @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
* translation (nbits sets into the "no BAR match" register)
* @vendor_id: PCI vendor ID
@@ -262,10 +261,9 @@ struct cdns_pcie_rc {
struct resource *cfg_res;
struct resource *bus_range;
void __iomem *cfg_base;
u32 max_regions;
u32 no_bar_nbits;
u16 vendor_id;
u16 device_id;
u32 vendor_id;
u32 device_id;
};
/**