Pull acpi-p-state into release branch
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@@ -116,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
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extern u16 ia64_acpiid_to_sapicid[];
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/*
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* Refer Intel ACPI _PDC support document for bit definitions
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*/
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#define ACPI_PDC_EST_CAPABILITY_SMP 0x8
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#endif /*__KERNEL__*/
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#endif /*_ASM_ACPI_H*/
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@@ -75,6 +75,8 @@
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#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
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#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
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#define PAL_VM_TR_READ 261 /* read contents of translation register */
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#define PAL_GET_PSTATE 262 /* get the current P-state */
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#define PAL_SET_PSTATE 263 /* set the P-state */
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#ifndef __ASSEMBLY__
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@@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
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return iprv.status;
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}
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/* Get the current P-state information */
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static inline s64
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ia64_pal_get_pstate (u64 *pstate_index)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
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*pstate_index = iprv.v0;
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return iprv.status;
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}
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/* Set the P-state */
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static inline s64
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ia64_pal_set_pstate (u64 pstate_index)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
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return iprv.status;
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}
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/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
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* suspended, but cache and TLB coherency is maintained.
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*/
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