ath9k: Program the RTC registers correctly
This patch programs the RTC registers of AR9100 chipsets correctly during chip reset. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@@ -1482,6 +1482,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
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u32 rst_flags;
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u32 tmpReg;
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if (AR_SREV_9100(ah)) {
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u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
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val &= ~AR_RTC_DERIVED_CLK_PERIOD;
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val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
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REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
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(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
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}
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REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
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AR_RTC_FORCE_WAKE_ON_INT);
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