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MIPS: Whitespace cleanup.

Forráskód böngészése 
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2013-01-22 12:59:30 +01:00
szülő 405ab01c70
commit 7034228792
764 fájl változott, egészen pontosan 11535 új sor hozzáadva és 11535 régi sor törölve
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/mips/pci/Makefile
Fájl megtekintése

@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
obj-$(CONFIG_CPU_XLR) += pci-xlr.o
obj-$(CONFIG_CPU_XLP) += pci-xlp.o
ifdef CONFIG_PCI_MSI
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
endif

28
arch/mips/pci/fixup-cobalt.c
Fájl megtekintése

@@ -94,14 +94,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
* --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
*
* On all machines prior to Q2, we had the STOP line disconnected
* from Galileo to VIA on PCI. The new Galileo does not function
* from Galileo to VIA on PCI. The new Galileo does not function
* correctly unless we have it connected.
*
* Therefore we must set the disconnect/retry cycle values to
* something sensible when using the new Galileo.
*/
printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
#if 0
if (dev->revision >= 0x10) {
@@ -149,30 +149,30 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
qube_raq_via_board_id_fixup);
static char irq_tab_qube1[] __initdata = {
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
[COBALT_PCICONF_ETH1] = 0
[COBALT_PCICONF_ETH1] = 0
};
static char irq_tab_cobalt[] __initdata = {
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = ETH0_IRQ,
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = ETH0_IRQ,
[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
[COBALT_PCICONF_ETH1] = ETH1_IRQ
[COBALT_PCICONF_ETH1] = ETH1_IRQ
};
static char irq_tab_raq2[] __initdata = {
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = ETH0_IRQ,
[COBALT_PCICONF_CPU] = 0,
[COBALT_PCICONF_ETH0] = ETH0_IRQ,
[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_VIA] = 0,
[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
[COBALT_PCICONF_ETH1] = ETH1_IRQ
[COBALT_PCICONF_ETH1] = ETH1_IRQ
};
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

2
arch/mips/pci/fixup-emma2rh.c
Fájl megtekintése

@@ -42,7 +42,7 @@
*
*/
#define MAX_SLOT_NUM 10
#define MAX_SLOT_NUM 10
static unsigned char irq_map[][5] __initdata = {
[3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
MARKEINS_PCI_IRQ_INTD, 0,},

8
arch/mips/pci/fixup-fuloong2e.c
Fájl megtekintése

@@ -6,9 +6,9 @@
* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
* Author: Fuxin Zhang, zhangfx@lemote.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
@@ -152,7 +152,7 @@ static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
/* disable read prefetch/write post buffers */
pci_write_config_byte(pdev, 0x41, 0x02);
/* use 3/4 as fifo thresh hold */
/* use 3/4 as fifo thresh hold */
pci_write_config_byte(pdev, 0x43, 0x0a);
pci_write_config_byte(pdev, 0x44, 0x00);

14
arch/mips/pci/fixup-ip32.c
Fájl megtekintése

@@ -22,13 +22,13 @@
#define INTC MACEPCI_SHARED1_IRQ
#define INTD MACEPCI_SHARED2_IRQ
static char irq_tab_mace[][5] __initdata = {
/* Dummy INT#A INT#B INT#C INT#D */
{0, 0, 0, 0, 0}, /* This is placeholder row - never used */
{0, SCSI0, SCSI0, SCSI0, SCSI0},
{0, SCSI1, SCSI1, SCSI1, SCSI1},
{0, INTA0, INTB, INTC, INTD},
{0, INTA1, INTC, INTD, INTB},
{0, INTA2, INTD, INTB, INTC},
/* Dummy INT#A INT#B INT#C INT#D */
{0, 0, 0, 0, 0}, /* This is placeholder row - never used */
{0, SCSI0, SCSI0, SCSI0, SCSI0},
{0, SCSI1, SCSI1, SCSI1, SCSI1},
{0, INTA0, INTB, INTC, INTD},
{0, INTA1, INTC, INTD, INTB},
{0, INTA2, INTD, INTB, INTC},
};

14
arch/mips/pci/fixup-lemote2f.c
Fájl megtekintése

@@ -31,7 +31,7 @@
/* all the pci device has the PCIA pin, check the datasheet. */
static char irq_tab[][5] __initdata = {
/* INTA INTB INTC INTD */
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0}, /* 11: Unused */
{0, 0, 0, 0, 0}, /* 12: Unused */
{0, 0, 0, 0, 0}, /* 13: Unused */
@@ -69,15 +69,15 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
case 2:
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
CS5536_IDE_INTR);
return CS5536_IDE_INTR; /* for IDE */
return CS5536_IDE_INTR; /* for IDE */
case 3:
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
CS5536_ACC_INTR);
return CS5536_ACC_INTR; /* for AUDIO */
case 4: /* for OHCI */
case 5: /* for EHCI */
case 6: /* for UDC */
case 7: /* for OTG */
return CS5536_ACC_INTR; /* for AUDIO */
case 4: /* for OHCI */
case 5: /* for EHCI */
case 6: /* for UDC */
case 7: /* for OTG */
pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
CS5536_USB_INTR);
return CS5536_USB_INTR;

14
arch/mips/pci/fixup-malta.c
Fájl megtekintése

@@ -12,7 +12,7 @@ static char pci_irq[5] = {
};
static char irq_tab[][5] __initdata = {
/* INTA INTB INTC INTD */
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
{0, 0, 0, 0, 0 }, /* 1: Unused */
{0, 0, 0, 0, 0 }, /* 2: Unused */
@@ -23,7 +23,7 @@ static char irq_tab[][5] __initdata = {
{0, 0, 0, 0, 0 }, /* 7: Unused */
{0, 0, 0, 0, 0 }, /* 8: Unused */
{0, 0, 0, 0, 0 }, /* 9: Unused */
{0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
{0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
{0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
{0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
{0, 0, 0, 0, 0 }, /* 13: Unused */
@@ -31,9 +31,9 @@ static char irq_tab[][5] __initdata = {
{0, 0, 0, 0, 0 }, /* 15: Unused */
{0, 0, 0, 0, 0 }, /* 16: Unused */
{0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
{0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
{0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
{0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
{0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
{0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
{0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
{0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
};
@@ -54,8 +54,8 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;
static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */
0, 0, 0, 3,
4, 5, 6, 7,
0, 0, 0, 3,
4, 5, 6, 7,
0, 9, 10, 11,
12, 0, 14, 15
};

224
arch/mips/pci/fixup-pmcmsp.c
Fájl megtekintése

@@ -48,117 +48,117 @@
#if defined(CONFIG_PMC_MSP7120_GW)
/* Garibaldi Board IRQ wiring to PCI slots */
static char irq_tab[][5] __initdata = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
{0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
{0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
};
#elif defined(CONFIG_PMC_MSP7120_EVAL)
/* MSP7120 Eval Board IRQ wiring to PCI slots */
static char irq_tab[][5] __initdata = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
{0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
{0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
{0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
{0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
{0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
{0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
};
#else
/* Unknown board -- don't assign any IRQs */
static char irq_tab[][5] __initdata = {
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
/* INTA INTB INTC INTD */
{0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
{0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
{0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
{0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
{0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
{0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
{0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
{0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
{0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
{0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
{0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
{0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
{0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
{0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
{0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
{0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
{0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
{0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
{0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
{0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
{0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
{0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
{0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
{0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
};
#endif
@@ -168,14 +168,14 @@ static char irq_tab[][5] __initdata = {
* _________________________________________________________________________
*
* DESCRIPTION: Perform platform specific device initialization at
* pci_enable_device() time.
* None are needed for the MSP7120 PCI Controller.
* pci_enable_device() time.
* None are needed for the MSP7120 PCI Controller.
*
* INPUTS: dev - structure describing the PCI device
* INPUTS: dev - structure describing the PCI device
*
* OUTPUTS: none
* OUTPUTS: none
*
* RETURNS: PCIBIOS_SUCCESSFUL
* RETURNS: PCIBIOS_SUCCESSFUL
*
****************************************************************************/
int pcibios_plat_dev_init(struct pci_dev *dev)
@@ -190,16 +190,16 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
*
* DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
*
* INPUTS: dev - unused
* slot - PCI slot. Identified by which bit of the AD[] bus
* drives the IDSEL line. AD[10] is 0, AD[31] is
* slot 21.
* pin - numbered using the scheme of the PCI_INTERRUPT_PIN
* field of the config header.
* INPUTS: dev - unused
* slot - PCI slot. Identified by which bit of the AD[] bus
* drives the IDSEL line. AD[10] is 0, AD[31] is
* slot 21.
* pin - numbered using the scheme of the PCI_INTERRUPT_PIN
* field of the config header.
*
* OUTPUTS: none
* OUTPUTS: none
*
* RETURNS: IRQ number
* RETURNS: IRQ number
*
****************************************************************************/
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

68
arch/mips/pci/fixup-sni.c
Fájl megtekintése

@@ -41,12 +41,12 @@
* Logic CL-GD5434 VGA is device 3.
*/
static char irq_tab_rm200[8][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* EISA bridge */
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* EISA bridge */
{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
{ ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
{ ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
{ INTB, INTB, INTB, INTB, INTB }, /* VGA */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
{ 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
@@ -58,20 +58,20 @@ static char irq_tab_rm200[8][5] __initdata = {
* The VGA card is optional for RM300 systems.
*/
static char irq_tab_rm300d[8][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* EISA bridge */
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* EISA bridge */
{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
{ 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
{ INTB, INTB, INTB, INTB, INTB }, /* VGA */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
{ 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
};
static char irq_tab_rm300e[5][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
{ SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
{ 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
{ 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
@@ -97,30 +97,30 @@ static char irq_tab_rm300e[5][5] __initdata = {
#define INTD PCIT_IRQ_INTD
static char irq_tab_pcit[13][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
{ SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */
{ SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 }, /* SCSI */
{ ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
{ 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTA, INTB, INTC, INTD }, /* Slot 1 */
{ 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
{ 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
{ 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
{ ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
{ 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTA, INTB, INTC, INTD }, /* Slot 1 */
{ 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
{ 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
{ 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
{ 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
};
static char irq_tab_pcit_cplus[13][5] __initdata = {
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
{ 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
{ 0, 0, 0, 0, 0 }, /* PCI-EISA */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
{ 0, INTB, INTC, INTD, INTA }, /* fixup */
/* INTA INTB INTC INTD */
{ 0, 0, 0, 0, 0 }, /* HOST bridge */
{ 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
{ 0, 0, 0, 0, 0 }, /* PCI-EISA */
{ 0, 0, 0, 0, 0 }, /* Unused */
{ 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
{ 0, INTB, INTC, INTD, INTA }, /* fixup */
};
static inline int is_rm300_revd(void)
@@ -146,18 +146,18 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
}
return irq_tab_pcit_cplus[slot][pin];
case SNI_BRD_PCI_TOWER:
return irq_tab_pcit[slot][pin];
return irq_tab_pcit[slot][pin];
case SNI_BRD_PCI_MTOWER:
if (is_rm300_revd())
return irq_tab_rm300d[slot][pin];
/* fall through */
if (is_rm300_revd())
return irq_tab_rm300d[slot][pin];
/* fall through */
case SNI_BRD_PCI_DESKTOP:
return irq_tab_rm200[slot][pin];
return irq_tab_rm200[slot][pin];
case SNI_BRD_PCI_MTOWER_CPLUS:
return irq_tab_rm300e[slot][pin];
return irq_tab_rm300e[slot][pin];
}
return 0;

2
arch/mips/pci/fixup-tb0219.c
Fájl megtekintése

@@ -1,7 +1,7 @@
/*
* fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
*
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
* Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify

2
arch/mips/pci/fixup-tb0287.c
Fájl megtekintése

@@ -1,7 +1,7 @@
/*
* fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
*
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
* Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by

2
arch/mips/pci/fixup-wrppmc.c
Fájl megtekintése

@@ -20,7 +20,7 @@
#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
/* 0 INTA INTB INTC INTD */
/* 0 INTA INTB INTC INTD */
[0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
[6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
};

16
arch/mips/pci/ops-bcm63xx.c
Fájl megtekintése

@@ -174,8 +174,8 @@ static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
}
struct pci_ops bcm63xx_pci_ops = {
.read = bcm63xx_pci_read,
.write = bcm63xx_pci_write
.read = bcm63xx_pci_read,
.write = bcm63xx_pci_write
};
#ifdef CONFIG_CARDBUS
@@ -370,8 +370,8 @@ static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
return fake_cb_bridge_read(where, size, val);
}
/* a configuration cycle for the device behind the cardbus
* bridge is actually done as a type 0 cycle on the primary
/* a configuration cycle for the device behind the cardbus
* bridge is actually done as a type 0 cycle on the primary
* bus. This means that only one device can be on the cardbus
* bus */
if (fake_cb_bridge_regs.bus_assigned &&
@@ -403,8 +403,8 @@ static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
}
struct pci_ops bcm63xx_cb_ops = {
.read = bcm63xx_cb_read,
.write = bcm63xx_cb_write,
.read = bcm63xx_cb_read,
.write = bcm63xx_cb_write,
};
/*
@@ -523,6 +523,6 @@ static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
struct pci_ops bcm63xx_pcie_ops = {
.read = bcm63xx_pcie_read,
.write = bcm63xx_pcie_write
.read = bcm63xx_pcie_read,
.write = bcm63xx_pcie_write
};

4
arch/mips/pci/ops-bonito64.c
Fájl megtekintése

@@ -26,7 +26,7 @@
#include <asm/mips-boards/bonito64.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
@@ -137,7 +137,7 @@ static int bonito64_pcibios_write(struct pci_bus *bus, unsigned int devfn,
data = val;
else {
if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
where, &data))
where, &data))
return -1;
if (size == 1)

24
arch/mips/pci/ops-gt64xxx_pci0.c
Fájl megtekintése

@@ -23,21 +23,21 @@
#include <asm/gt64120.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/*
* PCI configuration cycle AD bus definition
*/
/* Type 0 */
#define PCI_CFG_TYPE0_REG_SHF 0
#define PCI_CFG_TYPE0_FUNC_SHF 8
#define PCI_CFG_TYPE0_REG_SHF 0
#define PCI_CFG_TYPE0_FUNC_SHF 8
/* Type 1 */
#define PCI_CFG_TYPE1_REG_SHF 0
#define PCI_CFG_TYPE1_FUNC_SHF 8
#define PCI_CFG_TYPE1_DEV_SHF 11
#define PCI_CFG_TYPE1_BUS_SHF 16
#define PCI_CFG_TYPE1_REG_SHF 0
#define PCI_CFG_TYPE1_FUNC_SHF 8
#define PCI_CFG_TYPE1_DEV_SHF 11
#define PCI_CFG_TYPE1_BUS_SHF 16
static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
@@ -50,7 +50,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
@@ -87,7 +87,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
/* Clear bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
GT_INTRCAUSE_TARABORT0_BIT));
return -1;
}
@@ -106,7 +106,7 @@ static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
u32 data = 0;
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
where, &data))
where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
@@ -128,7 +128,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
data = val;
else {
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
devfn, where, &data))
devfn, where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
if (size == 1)
@@ -140,7 +140,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
}
if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
where, &data))
where, &data))
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;

2
arch/mips/pci/ops-lantiq.c
Fájl megtekintése

@@ -23,7 +23,7 @@
#define LTQ_PCI_CFG_DEVNUM_SHF 11
#define LTQ_PCI_CFG_FUNNUM_SHF 8
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,

2
arch/mips/pci/ops-loongson2.c
Fájl megtekintése

@@ -24,7 +24,7 @@
#include <cs5536/cs5536.h>
#endif
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define CFG_SPACE_REG(offset) \

22
arch/mips/pci/ops-msc.c
Fájl megtekintése

@@ -1,8 +1,8 @@
/*
* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
* All rights reserved.
* Authors: Carsten Langgaard <carstenl@mips.com>
* Maciej W. Rozycki <macro@mips.com>
* Maciej W. Rozycki <macro@mips.com>
* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can distribute it and/or modify it
@@ -28,21 +28,21 @@
#include <asm/mips-boards/msc01_pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/*
* PCI configuration cycle AD bus definition
*/
/* Type 0 */
#define PCI_CFG_TYPE0_REG_SHF 0
#define PCI_CFG_TYPE0_FUNC_SHF 8
#define PCI_CFG_TYPE0_REG_SHF 0
#define PCI_CFG_TYPE0_FUNC_SHF 8
/* Type 1 */
#define PCI_CFG_TYPE1_REG_SHF 0
#define PCI_CFG_TYPE1_FUNC_SHF 8
#define PCI_CFG_TYPE1_DEV_SHF 11
#define PCI_CFG_TYPE1_BUS_SHF 16
#define PCI_CFG_TYPE1_REG_SHF 0
#define PCI_CFG_TYPE1_FUNC_SHF 8
#define PCI_CFG_TYPE1_DEV_SHF 11
#define PCI_CFG_TYPE1_BUS_SHF 16
static int msc_pcibios_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
@@ -97,7 +97,7 @@ static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
return PCIBIOS_BAD_REGISTER_NUMBER;
if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
&data))
&data))
return -1;
if (size == 1)
@@ -124,7 +124,7 @@ static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
data = val;
else {
if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
where, &data))
where, &data))
return -1;
if (size == 1)

2
arch/mips/pci/ops-nile4.c
Fájl megtekintése

@@ -6,7 +6,7 @@
#include <asm/lasat/lasat.h>
#include <asm/nile4.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define LO(reg) (reg / 4)

434
arch/mips/pci/ops-pmcmsp.c
Fájl megtekintése

@@ -9,8 +9,8 @@
* Much of the code is derived from the original DDB5074 port by
* Geert Uytterhoeven <geert@sonycom.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@@ -57,18 +57,18 @@ static void pci_proc_init(void);
* _________________________________________________________________________
*
* DESCRIPTION: Prints the count of how many times each PCI
* interrupt has asserted. Can be invoked by the
* /proc filesystem.
* interrupt has asserted. Can be invoked by the
* /proc filesystem.
*
* INPUTS: page - part of STDOUT calculation
* off - part of STDOUT calculation
* count - part of STDOUT calculation
* data - unused
* INPUTS: page - part of STDOUT calculation
* off - part of STDOUT calculation
* count - part of STDOUT calculation
* data - unused
*
* OUTPUTS: start - new start location
* eof - end of file pointer
* OUTPUTS: start - new start location
* eof - end of file pointer
*
* RETURNS: len - STDOUT length
* RETURNS: len - STDOUT length
*
****************************************************************************/
static int read_msp_pci_counts(char *page, char **start, off_t off,
@@ -106,21 +106,21 @@ static int read_msp_pci_counts(char *page, char **start, off_t off,
* _________________________________________________________________________
*
* DESCRIPTION: Generates a configuration write cycle for debug purposes.
* The IDSEL line asserted and location and data written are
* immaterial. Just want to be able to prove that a
* configuration write can be correctly generated on the
* PCI bus. Intent is that this function by invocable from
* the /proc filesystem.
* The IDSEL line asserted and location and data written are
* immaterial. Just want to be able to prove that a
* configuration write can be correctly generated on the
* PCI bus. Intent is that this function by invocable from
* the /proc filesystem.
*
* INPUTS: page - part of STDOUT calculation
* off - part of STDOUT calculation
* count - part of STDOUT calculation
* data - unused
* INPUTS: page - part of STDOUT calculation
* off - part of STDOUT calculation
* count - part of STDOUT calculation
* data - unused
*
* OUTPUTS: start - new start location
* eof - end of file pointer
* OUTPUTS: start - new start location
* eof - end of file pointer
*
* RETURNS: len - STDOUT length
* RETURNS: len - STDOUT length
*
****************************************************************************/
static int gen_pci_cfg_wr(char *page, char **start, off_t off,
@@ -190,11 +190,11 @@ static int gen_pci_cfg_wr(char *page, char **start, off_t off,
*
* DESCRIPTION: Create entries in the /proc filesystem for debug access.
*
* INPUTS: none
* INPUTS: none
*
* OUTPUTS: none
* OUTPUTS: none
*
* RETURNS: none
* RETURNS: none
*
****************************************************************************/
static void pci_proc_init(void)
@@ -214,44 +214,44 @@ static DEFINE_SPINLOCK(bpci_lock);
* _________________________________________________________________________
*
* DESCRIPTION: Defines the address range that pciauto() will use to
* assign to the I/O BARs of PCI devices.
* assign to the I/O BARs of PCI devices.
*
* Use the start and end addresses of the MSP7120 PCI Host
* Controller I/O space, in the form that they appear on the
* PCI bus AFTER MSP7120 has performed address translation.
* Use the start and end addresses of the MSP7120 PCI Host
* Controller I/O space, in the form that they appear on the
* PCI bus AFTER MSP7120 has performed address translation.
*
* For I/O accesses, MSP7120 ignores OATRAN and maps I/O
* accesses into the bottom 0xFFF region of address space,
* so that is the range to put into the pci_io_resource
* struct.
* For I/O accesses, MSP7120 ignores OATRAN and maps I/O
* accesses into the bottom 0xFFF region of address space,
* so that is the range to put into the pci_io_resource
* struct.
*
* In MSP4200, the start address was 0x04 instead of the
* expected 0x00. Will just assume there was a good reason
* for this!
* In MSP4200, the start address was 0x04 instead of the
* expected 0x00. Will just assume there was a good reason
* for this!
*
* NOTES: Linux, by default, will assign I/O space to the lowest
* region of address space. Since MSP7120 and Linux,
* by default, have no offset in between how they map, the
* io_offset element of pci_controller struct should be set
* to zero.
* NOTES: Linux, by default, will assign I/O space to the lowest
* region of address space. Since MSP7120 and Linux,
* by default, have no offset in between how they map, the
* io_offset element of pci_controller struct should be set
* to zero.
* ELEMENTS:
* name - String used for a meaningful name.
* name - String used for a meaningful name.
*
* start - Start address of MSP7120's I/O space, as MSP7120 presents
* the address on the PCI bus.
* start - Start address of MSP7120's I/O space, as MSP7120 presents
* the address on the PCI bus.
*
* end - End address of MSP7120's I/O space, as MSP7120 presents
* the address on the PCI bus.
* end - End address of MSP7120's I/O space, as MSP7120 presents
* the address on the PCI bus.
*
* flags - Attributes indicating the type of resource. In this case,
* indicate I/O space.
* flags - Attributes indicating the type of resource. In this case,
* indicate I/O space.
*
****************************************************************************/
static struct resource pci_io_resource = {
.name = "pci IO space",
.start = 0x04,
.end = 0x0FFF,
.flags = IORESOURCE_IO /* I/O space */
.flags = IORESOURCE_IO /* I/O space */
};
/*****************************************************************************
@@ -260,26 +260,26 @@ static struct resource pci_io_resource = {
* _________________________________________________________________________
*
* DESCRIPTION: Defines the address range that pciauto() will use to
* assign to the memory BARs of PCI devices.
* assign to the memory BARs of PCI devices.
*
* The .start and .end values are dependent upon how address
* translation is performed by the OATRAN regiser.
* The .start and .end values are dependent upon how address
* translation is performed by the OATRAN regiser.
*
* The values to use for .start and .end are the values
* in the form they appear on the PCI bus AFTER MSP7120 has
* performed OATRAN address translation.
* The values to use for .start and .end are the values
* in the form they appear on the PCI bus AFTER MSP7120 has
* performed OATRAN address translation.
*
* ELEMENTS:
* name - String used for a meaningful name.
* name - String used for a meaningful name.
*
* start - Start address of MSP7120's memory space, as MSP7120 presents
* the address on the PCI bus.
* start - Start address of MSP7120's memory space, as MSP7120 presents
* the address on the PCI bus.
*
* end - End address of MSP7120's memory space, as MSP7120 presents
* the address on the PCI bus.
* end - End address of MSP7120's memory space, as MSP7120 presents
* the address on the PCI bus.
*
* flags - Attributes indicating the type of resource. In this case,
* indicate memory space.
* flags - Attributes indicating the type of resource. In this case,
* indicate memory space.
*
****************************************************************************/
static struct resource pci_mem_resource = {
@@ -295,17 +295,17 @@ static struct resource pci_mem_resource = {
* _________________________________________________________________________
*
* DESCRIPTION: PCI status interrupt handler. Updates the count of how
* many times each status bit has been set, then clears
* the status bits. If the appropriate macros are defined,
* these counts can be viewed via the /proc filesystem.
* many times each status bit has been set, then clears
* the status bits. If the appropriate macros are defined,
* these counts can be viewed via the /proc filesystem.
*
* INPUTS: irq - unused
* dev_id - unused
* pt_regs - unused
* INPUTS: irq - unused
* dev_id - unused
* pt_regs - unused
*
* OUTPUTS: none
* OUTPUTS: none
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* RETURNS: PCIBIOS_SUCCESSFUL - success
*
****************************************************************************/
static irqreturn_t bpci_interrupt(int irq, void *dev_id)
@@ -335,41 +335,41 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id)
* _________________________________________________________________________
*
* DESCRIPTION: Performs a PCI configuration access (rd or wr), then
* checks that the access succeeded by querying MSP7120's
* PCI status bits.
* checks that the access succeeded by querying MSP7120's
* PCI status bits.
*
* INPUTS:
* access_type - kind of PCI configuration cycle to perform
* (read or write). Legal values are
* PCI_ACCESS_WRITE and PCI_ACCESS_READ.
* access_type - kind of PCI configuration cycle to perform
* (read or write). Legal values are
* PCI_ACCESS_WRITE and PCI_ACCESS_READ.
*
* bus - pointer to the bus number of the device to
* be targeted for the configuration cycle.
* The only element of the pci_bus structure
* used is bus->number. This argument determines
* if the configuration access will be Type 0 or
* Type 1. Since MSP7120 assumes itself to be the
* PCI Host, any non-zero bus->number generates
* a Type 1 access.
* bus - pointer to the bus number of the device to
* be targeted for the configuration cycle.
* The only element of the pci_bus structure
* used is bus->number. This argument determines
* if the configuration access will be Type 0 or
* Type 1. Since MSP7120 assumes itself to be the
* PCI Host, any non-zero bus->number generates
* a Type 1 access.
*
* devfn - this is an 8-bit field. The lower three bits
* specify the function number of the device to
* be targeted for the configuration cycle, with
* all three-bit combinations being legal. The
* upper five bits specify the device number,
* with legal values being 10 to 31.
* devfn - this is an 8-bit field. The lower three bits
* specify the function number of the device to
* be targeted for the configuration cycle, with
* all three-bit combinations being legal. The
* upper five bits specify the device number,
* with legal values being 10 to 31.
*
* where - address within the Configuration Header
* space to access.
* where - address within the Configuration Header
* space to access.
*
* data - for write accesses, contains the data to
* write.
* data - for write accesses, contains the data to
* write.
*
* OUTPUTS:
* data - for read accesses, contains the value read.
* data - for read accesses, contains the value read.
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - access failure
*
****************************************************************************/
int msp_pcibios_config_access(unsigned char access_type,
@@ -429,7 +429,7 @@ int msp_pcibios_config_access(unsigned char access_type,
* for this Block Copy, called Block Copy 0 Fault (BC0F) and
* Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
* dedicated Block Copy block, so these two interrupts are now
* marked reserved. In case the Block Copy is resurrected in a
* marked reserved. In case the Block Copy is resurrected in a
* future design, maintain the code that treats these two interrupts
* specially.
*
@@ -439,7 +439,7 @@ int msp_pcibios_config_access(unsigned char access_type,
preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
/* Setup address that is to appear on PCI bus */
preg->config_addr = BPCI_CFGADDR_ENABLE |
preg->config_addr = BPCI_CFGADDR_ENABLE |
(bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
(dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
(where & 0xFC);
@@ -494,21 +494,21 @@ int msp_pcibios_config_access(unsigned char access_type,
* _________________________________________________________________________
*
* DESCRIPTION: Read a byte from PCI configuration address spac
* Since the hardware can't address 8 bit chunks
* directly, read a 32-bit chunk, then mask off extraneous
* bits.
* Since the hardware can't address 8 bit chunks
* directly, read a 32-bit chunk, then mask off extraneous
* bits.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
*
* OUTPUTS val - read data
* OUTPUTS val - read data
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - read access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - read access failure
*
****************************************************************************/
static int
@@ -541,22 +541,22 @@ msp_pcibios_read_config_byte(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
* Since the hardware can't address 16 bit chunks
* directly, read a 32-bit chunk, then mask off extraneous
* bits.
* Since the hardware can't address 16 bit chunks
* directly, read a 32-bit chunk, then mask off extraneous
* bits.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
*
* OUTPUTS val - read data
* OUTPUTS val - read data
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - read access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - read access failure
*
****************************************************************************/
static int
@@ -600,20 +600,20 @@ msp_pcibios_read_config_word(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Read a double word (32 bits) from PCI configuration
* address space.
* address space.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
* INPUTS bus - structure containing attributes for the PCI bus
* that the read is destined for.
* devfn - device/function combination that the read is
* destined for.
* where - register within the Configuration Header space
* to access.
*
* OUTPUTS val - read data
* OUTPUTS val - read data
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - read access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - read access failure
*
****************************************************************************/
static int
@@ -652,21 +652,21 @@ msp_pcibios_read_config_dword(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Write a byte to PCI configuration address space.
* Since the hardware can't address 8 bit chunks
* directly, a read-modify-write is performed.
* Since the hardware can't address 8 bit chunks
* directly, a read-modify-write is performed.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
*
* OUTPUTS none
* OUTPUTS none
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - write access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - write access failure
*
****************************************************************************/
static int
@@ -700,22 +700,22 @@ msp_pcibios_write_config_byte(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
* Since the hardware can't address 16 bit chunks
* directly, a read-modify-write is performed.
* Since the hardware can't address 16 bit chunks
* directly, a read-modify-write is performed.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
*
* OUTPUTS none
* OUTPUTS none
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - write access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - write access failure
*
****************************************************************************/
static int
@@ -753,21 +753,21 @@ msp_pcibios_write_config_word(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Write a double word (32-bits) to PCI configuration address
* space.
* space.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* val - value to write
*
* OUTPUTS none
* OUTPUTS none
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - write access failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* PCIBIOS_BAD_REGISTER_NUMBER - bad register address
* -1 - write access failure
*
****************************************************************************/
static int
@@ -794,22 +794,22 @@ msp_pcibios_write_config_dword(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Interface the PCI configuration read request with
* the appropriate function, based on how many bytes
* the read request is.
* the appropriate function, based on how many bytes
* the read request is.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* size - in units of bytes, should be 1, 2, or 4.
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* size - in units of bytes, should be 1, 2, or 4.
*
* OUTPUTS val - value read, with any extraneous bytes masked
* to zero.
* OUTPUTS val - value read, with any extraneous bytes masked
* to zero.
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - failure
*
****************************************************************************/
int
@@ -845,22 +845,22 @@ msp_pcibios_read_config(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: Interface the PCI configuration write request with
* the appropriate function, based on how many bytes
* the read request is.
* the appropriate function, based on how many bytes
* the read request is.
*
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* size - in units of bytes, should be 1, 2, or 4.
* val - value to write
* INPUTS bus - structure containing attributes for the PCI bus
* that the write is destined for.
* devfn - device/function combination that the write is
* destined for.
* where - register within the Configuration Header space
* to access.
* size - in units of bytes, should be 1, 2, or 4.
* val - value to write
*
* OUTPUTS: none
* OUTPUTS: none
*
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - failure
* RETURNS: PCIBIOS_SUCCESSFUL - success
* -1 - failure
*
****************************************************************************/
int
@@ -897,11 +897,11 @@ msp_pcibios_write_config(struct pci_bus *bus,
* _________________________________________________________________________
*
* DESCRIPTION: structure to abstract the hardware specific PCI
* configuration accesses.
* configuration accesses.
*
* ELEMENTS:
* read - function for Linux to generate PCI Configuration reads.
* write - function for Linux to generate PCI Configuration writes.
* read - function for Linux to generate PCI Configuration reads.
* write - function for Linux to generate PCI Configuration writes.
*
****************************************************************************/
struct pci_ops msp_pci_ops = {
@@ -917,27 +917,27 @@ struct pci_ops msp_pci_ops = {
* Describes the attributes of the MSP7120 PCI Host Controller
*
* ELEMENTS:
* pci_ops - abstracts the hardware specific PCI configuration
* accesses.
* pci_ops - abstracts the hardware specific PCI configuration
* accesses.
*
* mem_resource - address range pciauto() uses to assign to PCI device
* memory BARs.
* memory BARs.
*
* mem_offset - offset between how MSP7120 outbound PCI memory
* transaction addresses appear on the PCI bus and how Linux
* wants to configure memory BARs of the PCI devices.
* MSP7120 does nothing funky, so just set to zero.
* transaction addresses appear on the PCI bus and how Linux
* wants to configure memory BARs of the PCI devices.
* MSP7120 does nothing funky, so just set to zero.
*
* io_resource - address range pciauto() uses to assign to PCI device
* I/O BARs.
* I/O BARs.
*
* io_offset - offset between how MSP7120 outbound PCI I/O
* transaction addresses appear on the PCI bus and how
* Linux defaults to configure I/O BARs of the PCI devices.
* MSP7120 maps outbound I/O accesses into the bottom
* bottom 4K of PCI address space (and ignores OATRAN).
* Since the Linux default is to configure I/O BARs to the
* bottom 4K, no special offset is needed. Just set to zero.
* io_offset - offset between how MSP7120 outbound PCI I/O
* transaction addresses appear on the PCI bus and how
* Linux defaults to configure I/O BARs of the PCI devices.
* MSP7120 maps outbound I/O accesses into the bottom
* bottom 4K of PCI address space (and ignores OATRAN).
* Since the Linux default is to configure I/O BARs to the
* bottom 4K, no special offset is needed. Just set to zero.
*
****************************************************************************/
static struct pci_controller msp_pci_controller = {
@@ -955,7 +955,7 @@ static struct pci_controller msp_pci_controller = {
* _________________________________________________________________________
*
* DESCRIPTION: Initialize the PCI Host Controller and register it with
* Linux so Linux can seize control of the PCI bus.
* Linux so Linux can seize control of the PCI bus.
*
****************************************************************************/
void __init msp_pci_init(void)
@@ -979,7 +979,7 @@ void __init msp_pci_init(void)
*(unsigned long *)QFLUSH_REG_1 = 3;
/* Configure PCI Host Controller. */
preg->if_status = ~0; /* Clear cause register bits */
preg->if_status = ~0; /* Clear cause register bits */
preg->config_addr = 0; /* Clear config access */
preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */

2
arch/mips/pci/ops-rc32434.c
Fájl megtekintése

@@ -35,7 +35,7 @@
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1

8
arch/mips/pci/ops-sni.c
Fájl megtekintése

@@ -14,8 +14,8 @@
/*
* It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
* address are decoded. We therefore manually have to reject attempts at
* reading outside this range. Being on the paranoid side we only do this
* address are decoded. We therefore manually have to reject attempts at
* reading outside this range. Being on the paranoid side we only do this
* test for bus 0 and hope forwarding and decoding work properly for any
* subordinated busses.
*
@@ -31,8 +31,8 @@ static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
*(volatile u32 *)PCIMT_CONFIG_ADDRESS =
((busno & 0xff) << 16) |
((devfn & 0xff) << 8) |
(reg & 0xfc);
((devfn & 0xff) << 8) |
(reg & 0xfc);
return PCIBIOS_SUCCESSFUL;
}

8
arch/mips/pci/ops-tx4927.c
Fájl megtekintése

@@ -2,16 +2,16 @@
* Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
*
* Based on linux/arch/mips/pci/ops-tx4938.c,
* linux/arch/mips/pci/fixup-rbtx4938.c,
* linux/arch/mips/txx9/rbtx4938/setup.c,
* linux/arch/mips/pci/fixup-rbtx4938.c,
* linux/arch/mips/txx9/rbtx4938/setup.c,
* and RBTX49xx patch from CELF patch archive.
*
* 2003-2005 (c) MontaVista Software, Inc.
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/

6
arch/mips/pci/ops-vr41xx.c
Fájl megtekintése

@@ -33,7 +33,7 @@
#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
static inline int set_pci_configuration_address(unsigned char number,
unsigned int devfn, int where)
unsigned int devfn, int where)
{
if (number == 0) {
/*
@@ -59,7 +59,7 @@ static inline int set_pci_configuration_address(unsigned char number,
}
static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, uint32_t *val)
int size, uint32_t *val)
{
uint32_t data;
@@ -87,7 +87,7 @@ static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
}
static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, uint32_t val)
int size, uint32_t val)
{
uint32_t data;
int shift;

6
arch/mips/pci/pci-alchemy.c
Fájl megtekintése

@@ -29,7 +29,7 @@
#define PCI_ACCESS_WRITE 1
struct alchemy_pci_context {
struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
void __iomem *regs; /* ctrl base */
/* tools for wired entry for config space access */
unsigned long last_elo0;
@@ -381,7 +381,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
ret = -ENODEV;
goto out1;
}
@@ -482,7 +482,7 @@ out:
static struct platform_driver alchemy_pcictl_driver = {
.probe = alchemy_pci_probe,
.driver = {
.driver = {
.name = "alchemy-pci",
.owner = THIS_MODULE,
},

20
arch/mips/pci/pci-ar724x.c
Fájl megtekintése

@@ -177,22 +177,22 @@ static struct pci_ops ar724x_pci_ops = {
};
static struct resource ar724x_io_resource = {
.name = "PCI IO space",
.start = 0,
.end = 0,
.flags = IORESOURCE_IO,
.name = "PCI IO space",
.start = 0,
.end = 0,
.flags = IORESOURCE_IO,
};
static struct resource ar724x_mem_resource = {
.name = "PCI memory space",
.start = AR724X_PCI_MEM_BASE,
.end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
.name = "PCI memory space",
.start = AR724X_PCI_MEM_BASE,
.end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct pci_controller ar724x_pci_controller = {
.pci_ops = &ar724x_pci_ops,
.io_resource = &ar724x_io_resource,
.pci_ops = &ar724x_pci_ops,
.io_resource = &ar724x_io_resource,
.mem_resource = &ar724x_mem_resource,
};

8
arch/mips/pci/pci-bcm1480.c
Fájl megtekintése

@@ -54,8 +54,8 @@
static void *cfg_space;
#define PCI_BUS_ENABLED 1
#define PCI_DEVICE_MODE 2
#define PCI_BUS_ENABLED 1
#define PCI_DEVICE_MODE 2
static int bcm1480_bus_status;
@@ -194,7 +194,7 @@ struct pci_controller bcm1480_controller = {
.pci_ops = &bcm1480_pci_ops,
.mem_resource = &bcm1480_mem_resource,
.io_resource = &bcm1480_io_resource,
.io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
.io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
};
@@ -227,7 +227,7 @@ static int __init bcm1480_pcibios_init(void)
PCI_COMMAND));
if (!(cmdreg & PCI_COMMAND_MASTER)) {
printk
("PCI: Skipping PCI probe. Bus is not initialized.\n");
("PCI: Skipping PCI probe. Bus is not initialized.\n");
iounmap(cfg_space);
return 1; /* XXX */
}

6
arch/mips/pci/pci-bcm1480ht.c
Fájl megtekintése

@@ -53,8 +53,8 @@
static void *ht_cfg_space;
#define PCI_BUS_ENABLED 1
#define PCI_DEVICE_MODE 2
#define PCI_BUS_ENABLED 1
#define PCI_DEVICE_MODE 2
static int bcm1480ht_bus_status;
@@ -191,7 +191,7 @@ struct pci_controller bcm1480ht_controller = {
.io_resource = &bcm1480ht_io_resource,
.index = 1,
.get_busno = bcm1480ht_pcibios_get_busno,
.io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
.io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
};
static int __init bcm1480ht_pcibios_init(void)

2
arch/mips/pci/pci-bcm47xx.c
Fájl megtekintése

@@ -91,7 +91,7 @@ static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
int pcibios_plat_dev_init(struct pci_dev *dev)
{
#ifdef CONFIG_BCM47XX_SSB
if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
return bcm47xx_pcibios_plat_dev_init_ssb(dev);
else
#endif

62
arch/mips/pci/pci-bcm63xx.c
Fájl megtekintése

@@ -25,21 +25,21 @@
int bcm63xx_pci_enabled;
static struct resource bcm_pci_mem_resource = {
.name = "bcm63xx PCI memory space",
.start = BCM_PCI_MEM_BASE_PA,
.end = BCM_PCI_MEM_END_PA,
.flags = IORESOURCE_MEM
.name = "bcm63xx PCI memory space",
.start = BCM_PCI_MEM_BASE_PA,
.end = BCM_PCI_MEM_END_PA,
.flags = IORESOURCE_MEM
};
static struct resource bcm_pci_io_resource = {
.name = "bcm63xx PCI IO space",
.start = BCM_PCI_IO_BASE_PA,
.name = "bcm63xx PCI IO space",
.start = BCM_PCI_IO_BASE_PA,
#ifdef CONFIG_CARDBUS
.end = BCM_PCI_IO_HALF_PA,
.end = BCM_PCI_IO_HALF_PA,
#else
.end = BCM_PCI_IO_END_PA,
.end = BCM_PCI_IO_END_PA,
#endif
.flags = IORESOURCE_IO
.flags = IORESOURCE_IO
};
struct pci_controller bcm63xx_controller = {
@@ -55,17 +55,17 @@ struct pci_controller bcm63xx_controller = {
*/
#ifdef CONFIG_CARDBUS
static struct resource bcm_cb_mem_resource = {
.name = "bcm63xx Cardbus memory space",
.start = BCM_CB_MEM_BASE_PA,
.end = BCM_CB_MEM_END_PA,
.flags = IORESOURCE_MEM
.name = "bcm63xx Cardbus memory space",
.start = BCM_CB_MEM_BASE_PA,
.end = BCM_CB_MEM_END_PA,
.flags = IORESOURCE_MEM
};
static struct resource bcm_cb_io_resource = {
.name = "bcm63xx Cardbus IO space",
.start = BCM_PCI_IO_HALF_PA + 1,
.end = BCM_PCI_IO_END_PA,
.flags = IORESOURCE_IO
.name = "bcm63xx Cardbus IO space",
.start = BCM_PCI_IO_HALF_PA + 1,
.end = BCM_PCI_IO_END_PA,
.flags = IORESOURCE_IO
};
struct pci_controller bcm63xx_cb_controller = {
@@ -76,17 +76,17 @@ struct pci_controller bcm63xx_cb_controller = {
#endif
static struct resource bcm_pcie_mem_resource = {
.name = "bcm63xx PCIe memory space",
.start = BCM_PCIE_MEM_BASE_PA,
.end = BCM_PCIE_MEM_END_PA,
.flags = IORESOURCE_MEM,
.name = "bcm63xx PCIe memory space",
.start = BCM_PCIE_MEM_BASE_PA,
.end = BCM_PCIE_MEM_END_PA,
.flags = IORESOURCE_MEM,
};
static struct resource bcm_pcie_io_resource = {
.name = "bcm63xx PCIe IO space",
.start = 0,
.end = 0,
.flags = 0,
.name = "bcm63xx PCIe IO space",
.start = 0,
.end = 0,
.flags = 0,
};
struct pci_controller bcm63xx_pcie_controller = {
@@ -111,7 +111,7 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
u32 tmp;
tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
}
@@ -211,7 +211,7 @@ static int __init bcm63xx_register_pci(void)
* first bytes to access it from CPU.
*
* this means that no io access from CPU should happen while
* we do a configuration cycle, but there's no way we can add
* we do a configuration cycle, but there's no way we can add
* a spinlock for each io access, so this is currently kind of
* broken on SMP.
*/
@@ -244,9 +244,9 @@ static int __init bcm63xx_register_pci(void)
bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
#endif
/* setup local bus to PCI access (IO memory), we have only 1
* IO window for both PCI and cardbus, but it cannot handle
* both at the same time, assume standard PCI for now, if
/* setup local bus to PCI access (IO memory), we have only 1
* IO window for both PCI and cardbus, but it cannot handle
* both at the same time, assume standard PCI for now, if
* cardbus card has IO zone, PCI fixup will change window to
* cardbus */
val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
@@ -284,7 +284,7 @@ static int __init bcm63xx_register_pci(void)
bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
}
/* change host bridge retry counter to infinite number of
/* change host bridge retry counter to infinite number of
* retry, needed for some broadcom wifi cards with Silicon
* Backplane bus where access to srom seems very slow */
val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);

2
arch/mips/pci/pci-bcm63xx.h
Fájl megtekintése

@@ -7,7 +7,7 @@
#include <bcm63xx_dev_pci.h>
/*
* Cardbus shares the PCI bus, but has no IDSEL, so a special id is
* Cardbus shares the PCI bus, but has no IDSEL, so a special id is
* reserved for it. If you have a standard PCI device at this id, you
* need to change the following definition.
*/

8
arch/mips/pci/pci-ip27.c
Fájl megtekintése

@@ -30,7 +30,7 @@
/*
* XXX: No kmalloc available when we do our crosstalk scan,
* we should try to move it later in the boot process.
* we should try to move it later in the boot process.
*/
static struct bridge_controller bridges[MAX_PCI_BUSSES];
@@ -103,7 +103,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
* swap pio's to pci mem and io space (big windows)
*/
bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
BRIDGE_CTRL_MEM_SWAP;
BRIDGE_CTRL_MEM_SWAP;
#ifdef CONFIG_PAGE_SIZE_4KB
bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
#else /* 16kB or larger */
@@ -123,7 +123,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
bc->pci_int[slot] = -1;
}
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
bridge->b_wid_tflush; /* wait until Bridge PIO complete */
bc->base = bridge;
@@ -184,7 +184,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
}
/*
* Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
* Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
* to find the slot number in sense of the bridge device register.
* XXX This also means multiple devices might rely on conflicting bridge
* settings.

6
arch/mips/pci/pci-ip32.c
Fájl megtekintése

@@ -18,9 +18,9 @@
/*
* Handle errors from the bridge. This includes master and target aborts,
* various command and address errors, and the interrupt test. This gets
* registered on the bridge error irq. It's conceivable that some of these
* conditions warrant a panic. Anybody care to say which ones?
* various command and address errors, and the interrupt test. This gets
* registered on the bridge error irq. It's conceivable that some of these
* conditions warrant a panic. Anybody care to say which ones?
*/
static irqreturn_t macepci_error(int irq, void *dev)
{

26
arch/mips/pci/pci-lasat.c
Fájl megtekintése

@@ -51,15 +51,15 @@ static int __init lasat_pci_setup(void)
arch_initcall(lasat_pci_setup);
#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
@@ -69,13 +69,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
case 3:
return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
case 4:
return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
case 5:
return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
case 6:
return LASAT_IRQ_HDC; /* IDE controller */
return LASAT_IRQ_HDC; /* IDE controller */
default:
return 0xff; /* Illegal */
return 0xff; /* Illegal */
}
return -1;

30
arch/mips/pci/pci-octeon.c
Fájl megtekintése

@@ -30,8 +30,8 @@
* addresses. Use PCI endian swapping 1 so no address swapping is
* necessary. The Linux io routines will endian swap the data.
*/
#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
@@ -68,10 +68,10 @@ enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
*
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @pin: The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* as it goes through each bridge.
* Returns Interrupt number for the device
*/
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -120,8 +120,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
/* Enable the PCIe normal error reporting */
config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
/* Find the Advanced Error Reporting capability */
@@ -226,10 +226,10 @@ const char *octeon_get_pci_interrupts(void)
*
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @pin: The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* as it goes through each bridge.
* Returns Interrupt number for the device
*/
int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
@@ -404,8 +404,8 @@ static void octeon_pci_initialize(void)
ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
ctl_status_2.s.bb1 = 1; /* BAR1 is big */
ctl_status_2.s.bb0 = 1; /* BAR0 is big */
ctl_status_2.s.bb1 = 1; /* BAR1 is big */
ctl_status_2.s.bb0 = 1; /* BAR0 is big */
}
octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
@@ -446,7 +446,7 @@ static void octeon_pci_initialize(void)
* count. [1..31] and 0=32. NOTE: If the user
* programs these bits beyond the Designed Maximum
* outstanding count, then the designed maximum table
* depth will be used instead. No additional
* depth will be used instead. No additional
* Deferred/Split transactions will be accepted if
* this outstanding maximum count is
* reached. Furthermore, no additional deferred/split
@@ -456,7 +456,7 @@ static void octeon_pci_initialize(void)
cfg19.s.tdomc = 4;
/*
* Master Deferred Read Request Outstanding Max Count
* (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
* (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
* cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
* 5 2 110 6 3 111 7 3 For example, if these bits are
* programmed to 100, the core can support 2 DAC
@@ -550,7 +550,7 @@ static void octeon_pci_initialize(void)
/*
* Affects PCI performance when OCTEON services reads to its
* BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
* BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
* 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
* PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
* these values need to be changed so they won't possibly prefetch off

6
arch/mips/pci/pci-rc32434.c
Fájl megtekintése

@@ -33,7 +33,7 @@
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/* define an unsigned array for the PCI registers */
@@ -82,11 +82,11 @@ extern struct pci_ops rc32434_pci_ops;
#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
#define PCI_IO1_END \
#define PCI_IO1_END \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
#define PCI_IO2_START \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
#define PCI_IO2_END \
#define PCI_IO2_END \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
struct pci_controller rc32434_controller2;

8
arch/mips/pci/pci-sb1250.c
Fájl megtekintése

@@ -55,9 +55,9 @@
static void *cfg_space;
#define PCI_BUS_ENABLED 1
#define LDT_BUS_ENABLED 2
#define PCI_DEVICE_MODE 4
#define PCI_BUS_ENABLED 1
#define LDT_BUS_ENABLED 2
#define PCI_DEVICE_MODE 4
static int sb1250_bus_status;
@@ -239,7 +239,7 @@ static int __init sb1250_pcibios_init(void)
PCI_COMMAND));
if (!(cmdreg & PCI_COMMAND_MASTER)) {
printk
("PCI: Skipping PCI probe. Bus is not initialized.\n");
("PCI: Skipping PCI probe. Bus is not initialized.\n");
iounmap(cfg_space);
return 0;
}

22
arch/mips/pci/pci-vr41xx.c
Fájl megtekintése

@@ -69,17 +69,17 @@ static struct pci_target_address_window pci_target_window1 = {
};
static struct resource pci_mem_resource = {
.name = "PCI Memory resources",
.start = PCI_MEM_RESOURCE_START,
.end = PCI_MEM_RESOURCE_END,
.flags = IORESOURCE_MEM,
.name = "PCI Memory resources",
.start = PCI_MEM_RESOURCE_START,
.end = PCI_MEM_RESOURCE_END,
.flags = IORESOURCE_MEM,
};
static struct resource pci_io_resource = {
.name = "PCI I/O resources",
.start = PCI_IO_RESOURCE_START,
.end = PCI_IO_RESOURCE_END,
.flags = IORESOURCE_IO,
.name = "PCI I/O resources",
.start = PCI_IO_RESOURCE_START,
.end = PCI_IO_RESOURCE_END,
.flags = IORESOURCE_IO,
};
static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
@@ -97,7 +97,7 @@ static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
};
static struct pci_controller vr41xx_pci_controller = {
.pci_ops = &vr41xx_pci_ops,
.pci_ops = &vr41xx_pci_ops,
.mem_resource = &pci_mem_resource,
.io_resource = &pci_io_resource,
};
@@ -148,7 +148,7 @@ static int __init vr41xx_pciu_init(void)
else if ((vtclock / 2) < pci_clock_max)
pciu_write(PCICLKSELREG, HALF_VTCLOCK);
else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
(vtclock / 3) < pci_clock_max)
(vtclock / 3) < pci_clock_max)
pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
else if ((vtclock / 4) < pci_clock_max)
pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
@@ -281,7 +281,7 @@ static int __init vr41xx_pciu_init(void)
pciu_write(PCIAPCNTREG, val);
pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
PCI_COMMAND_SERR);
/* Clear bus error */

2
arch/mips/pci/pci-vr41xx.h
Fájl megtekintése

@@ -1,7 +1,7 @@
/*
* pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
*
* Copyright (C) 2002 MontaVista Software Inc.
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Yoichi Yuasa <source@mvista.com>
* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
*

32
arch/mips/pci/pci-xlp.c
Fájl megtekintése

@@ -55,7 +55,7 @@
static void *pci_config_base;
#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
/* PCI ops */
static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
@@ -135,26 +135,26 @@ struct pci_ops nlm_pci_ops = {
};
static struct resource nlm_pci_mem_resource = {
.name = "XLP PCI MEM",
.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
.end = 0xdfffffffUL,
.flags = IORESOURCE_MEM,
.name = "XLP PCI MEM",
.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
.end = 0xdfffffffUL,
.flags = IORESOURCE_MEM,
};
static struct resource nlm_pci_io_resource = {
.name = "XLP IO MEM",
.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
.end = 0x17ffffffUL,
.flags = IORESOURCE_IO,
.name = "XLP IO MEM",
.start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
.end = 0x17ffffffUL,
.flags = IORESOURCE_IO,
};
struct pci_controller nlm_pci_controller = {
.index = 0,
.pci_ops = &nlm_pci_ops,
.mem_resource = &nlm_pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &nlm_pci_io_resource,
.io_offset = 0x00000000UL,
.index = 0,
.pci_ops = &nlm_pci_ops,
.mem_resource = &nlm_pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &nlm_pci_io_resource,
.io_offset = 0x00000000UL,
};
static int get_irq_vector(const struct pci_dev *dev)
@@ -232,7 +232,7 @@ static int __init pcibios_init(void)
pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
/* Extend IO port for memory mapped io */
ioport_resource.start = 0;
ioport_resource.start = 0;
ioport_resource.end = ~0;
xlp_enable_pci_bswap();

34
arch/mips/pci/pci-xlr.c
Fájl megtekintése

@@ -56,7 +56,7 @@
static void *pci_config_base;
#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
/* PCI ops */
static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
@@ -136,26 +136,26 @@ struct pci_ops nlm_pci_ops = {
};
static struct resource nlm_pci_mem_resource = {
.name = "XLR PCI MEM",
.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
.end = 0xdfffffffUL,
.flags = IORESOURCE_MEM,
.name = "XLR PCI MEM",
.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
.end = 0xdfffffffUL,
.flags = IORESOURCE_MEM,
};
static struct resource nlm_pci_io_resource = {
.name = "XLR IO MEM",
.start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
.end = 0x100fffffUL,
.flags = IORESOURCE_IO,
.name = "XLR IO MEM",
.start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
.end = 0x100fffffUL,
.flags = IORESOURCE_IO,
};
struct pci_controller nlm_pci_controller = {
.index = 0,
.pci_ops = &nlm_pci_ops,
.mem_resource = &nlm_pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &nlm_pci_io_resource,
.io_offset = 0x00000000UL,
.index = 0,
.pci_ops = &nlm_pci_ops,
.mem_resource = &nlm_pci_mem_resource,
.mem_offset = 0x00000000UL,
.io_resource = &nlm_pci_io_resource,
.io_offset = 0x00000000UL,
};
/*
@@ -259,7 +259,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
MSI_ADDR_REDIRECTION_CPU;
msg.data = MSI_DATA_TRIGGER_EDGE |
MSI_DATA_LEVEL_ASSERT |
MSI_DATA_LEVEL_ASSERT |
MSI_DATA_DELIVERY_FIXED;
ret = irq_set_msi_desc(irq, desc);
@@ -344,7 +344,7 @@ static int __init pcibios_init(void)
pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
/* Extend IO port for memory mapped io */
ioport_resource.start = 0;
ioport_resource.start = 0;
ioport_resource.end = ~0;
set_io_port_base(CKSEG1);

4
arch/mips/pci/pci.c
Fájl megtekintése

@@ -1,6 +1,6 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*

58
arch/mips/pci/pcie-octeon.c
Fájl megtekintése

@@ -43,7 +43,7 @@ union cvmx_pcie_address {
uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 1 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t es:2; /* Endian swap = 1 */
@@ -74,7 +74,7 @@ union cvmx_pcie_address {
uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 2 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t es:2; /* Endian swap = 1 */
@@ -85,7 +85,7 @@ union cvmx_pcie_address {
uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 3-6 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t address:36; /* PCIe Mem address */
@@ -166,7 +166,7 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
* Read a PCIe config space register indirectly. This is used for
* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
*
* @pcie_port: PCIe port to read from
* @pcie_port: PCIe port to read from
* @cfg_offset: Address to read
*
* Returns Value read
@@ -194,9 +194,9 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
* Write a PCIe config space register indirectly. This is used for
* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
*
* @pcie_port: PCIe port to write to
* @pcie_port: PCIe port to write to
* @cfg_offset: Address to write
* @val: Value to write
* @val: Value to write
*/
static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
uint32_t val)
@@ -222,7 +222,7 @@ static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
* @pcie_port: PCIe port to access
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
*
* Returns 64bit Octeon IO address
@@ -259,7 +259,7 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
@@ -281,7 +281,7 @@ static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
@@ -303,7 +303,7 @@ static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
@@ -325,7 +325,7 @@ static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
@@ -344,7 +344,7 @@ static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
@@ -363,7 +363,7 @@ static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
* @fn: Device sub function
* @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
@@ -883,14 +883,14 @@ retry:
/* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
/* Setup Mem access SubDIDs */
mem_access_subid.u64 = 0;
mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
@@ -926,7 +926,7 @@ retry:
bar1_index.u32 = 0;
bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.end_swp = 1; /* Endian Swap mode */
bar1_index.s.addr_v = 1; /* Valid entry */
@@ -1342,11 +1342,11 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
/* Setup Mem access SubDIDs */
mem_access_subid.u64 = 0;
mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
/* PCIe Adddress Bits <63:34>. */
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
mem_access_subid.cn68xx.ba = 0;
@@ -1409,7 +1409,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
bar1_index.u64 = 0;
bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.end_swp = 1; /* Endian Swap mode */
bar1_index.s.addr_v = 1; /* Valid entry */
@@ -1458,10 +1458,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
*
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* enumerates through all the bridges and figures out the
* slot on Bus 0 where this device eventually hooks to.
* @pin: The PCI interrupt pin read from the device, then swizzled
* as it goes through each bridge.
* as it goes through each bridge.
* Returns Interrupt number for the device
*/
int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
@@ -1503,7 +1503,7 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
return pin - 1 + OCTEON_IRQ_PCI_INT0;
}
static void set_cfg_read_retry(u32 retry_cnt)
static void set_cfg_read_retry(u32 retry_cnt)
{
union cvmx_pemx_ctl_status pemx_ctl;
pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
@@ -1931,7 +1931,7 @@ static int __init octeon_pcie_setup(void)
OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
if (sriox_status_reg.s.srio) {
srio_war15205 += 1; /* Port is SRIO */
srio_war15205 += 1; /* Port is SRIO */
port = 0;
}
}
@@ -2004,7 +2004,7 @@ static int __init octeon_pcie_setup(void)
OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
if (sriox_status_reg.s.srio) {
srio_war15205 += 1; /* Port is SRIO */
srio_war15205 += 1; /* Port is SRIO */
port = 1;
}
}