MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
@@ -13,5 +13,5 @@ cflags-$(CONFIG_CPU_XLP) += $(call cc-option,-march=xlp,-march=mips64r2)
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#
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# NETLOGIC processor support
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#
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platform-$(CONFIG_NLM_COMMON) += netlogic/
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load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
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platform-$(CONFIG_NLM_COMMON) += netlogic/
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load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
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@@ -69,7 +69,7 @@
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#else
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#define SMP_IRQ_MASK 0
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#endif
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#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
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#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
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(1ull << IRQ_FMN))
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struct nlm_pic_irq {
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@@ -107,7 +107,7 @@ static void xlp_pic_mask_ack(struct irq_data *d)
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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uint64_t mask = 1ull << pd->picirq;
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write_c0_eirr(mask); /* ack by writing EIRR */
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write_c0_eirr(mask); /* ack by writing EIRR */
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}
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static void xlp_pic_unmask(struct irq_data *d)
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@@ -49,12 +49,12 @@
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#include <asm/netlogic/xlp-hal/sys.h>
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#include <asm/netlogic/xlp-hal/cpucontrol.h>
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#define CP0_EBASE $15
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#define CP0_EBASE $15
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#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
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XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
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SYS_CPU_NONCOHERENT_MODE * 4
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#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
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#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
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/* Enable XLP features and workarounds in the LSU */
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.macro xlp_config_lsu
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@@ -85,7 +85,7 @@
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li t0, LSU_DEBUG_DATA0
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li t1, LSU_DEBUG_ADDR
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li t2, 0 /* index */
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li t3, 0x1000 /* loop count */
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li t3, 0x1000 /* loop count */
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1:
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sll v0, t2, 5
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mtcr zero, t0
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@@ -134,7 +134,7 @@ FEXPORT(nlm_reset_entry)
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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@@ -235,7 +235,7 @@ EXPORT(nlm_reset_entry_end)
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FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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xlp_config_lsu
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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SAVE_ALL
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sync
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/* find the location to which nlm_boot_siblings was relocated */
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@@ -301,13 +301,13 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
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*/
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li t0, 0x400
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mfcr t1, t0
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li t2, 6 /* XLR thread mode mask */
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li t2, 6 /* XLR thread mode mask */
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nor t3, t2, zero
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and t2, t1, t2 /* t2 - current thread mode */
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li v0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
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sll v1, 1
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beq v1, t2, 1f /* same as request value */
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beq v1, t2, 1f /* same as request value */
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nop /* nothing to do */
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and t2, t1, t3 /* mask out old thread mode */
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@@ -20,7 +20,7 @@
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
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ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
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1 0 0 0x16000000 0x01000000>; // GBU chipselects
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serial0: serial@30000 {
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@@ -111,8 +111,8 @@ unsigned int nlm_get_core_frequency(int node, int core)
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dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
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pll_divf = ((rstval >> 10) & 0x7f) + 1;
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pll_divr = ((rstval >> 8) & 0x3) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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ext_div = ((rstval >> 30) & 0x3) + 1;
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dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
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num = 800000000ULL * pll_divf;
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denom = 3 * pll_divr * ext_div * dfs_div;
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@@ -52,7 +52,7 @@ static void nlm_usb_intr_en(int node, int port)
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port_addr = nlm_get_usb_regbase(node, port);
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val = nlm_read_usb_reg(port_addr, USB_INT_EN);
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val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
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USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
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USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
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USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
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nlm_write_usb_reg(port_addr, USB_INT_EN, val);
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}
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@@ -164,8 +164,8 @@ static void setup_cpu_fmninfo(struct xlr_fmn_info *cpu, int num_core)
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int i, j;
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for (i = 0; i < num_core; i++) {
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cpu[i].start_stn_id = (8 * i);
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cpu[i].end_stn_id = (8 * i + 8);
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cpu[i].start_stn_id = (8 * i);
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cpu[i].end_stn_id = (8 * i + 8);
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for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++)
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xlr_board_fmn_config.bucket_size[j] = 32;
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@@ -36,7 +36,7 @@ static struct mtd_partition xlr_nor_parts[] = {
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{
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.name = "User FS",
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.offset = 0x800000,
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.size = MTDPART_SIZ_FULL,
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.size = MTDPART_SIZ_FULL,
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}
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};
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@@ -46,13 +46,13 @@ static struct mtd_partition xlr_nor_parts[] = {
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static struct mtd_partition xlr_nand_parts[] = {
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{
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.name = "Root Filesystem",
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.offset = 64 * 64 * 2048,
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.offset = 64 * 64 * 2048,
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.size = 432 * 64 * 2048,
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},
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{
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.name = "Home Filesystem",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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@@ -74,8 +74,8 @@ static struct platform_device xlr_nor_dev = {
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.dev = {
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.platform_data = &xlr_nor_data,
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},
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.num_resources = ARRAY_SIZE(xlr_nor_res),
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.resource = xlr_nor_res,
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.num_resources = ARRAY_SIZE(xlr_nor_res),
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.resource = xlr_nor_res,
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};
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const char *xlr_part_probes[] = { "cmdlinepart", NULL };
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@@ -162,18 +162,18 @@ int xls_platform_usb_init(void)
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nlm_write_reg(usb_mmio, 50, 0x1f000000);
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/* Enable ports */
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nlm_write_reg(usb_mmio, 1, 0x07000500);
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nlm_write_reg(usb_mmio, 1, 0x07000500);
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val = nlm_read_reg(gpio_mmio, 21);
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if (((val >> 22) & 0x01) == 0) {
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pr_info("Detected USB Device mode - Not supported!\n");
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nlm_write_reg(usb_mmio, 0, 0x01000000);
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nlm_write_reg(usb_mmio, 0, 0x01000000);
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return 0;
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}
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pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
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/* Clear reset, host mode */
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nlm_write_reg(usb_mmio, 0, 0x02000000);
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nlm_write_reg(usb_mmio, 0, 0x02000000);
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/* Memory resource for various XLS usb ports */
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usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
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@@ -221,8 +221,8 @@ static struct resource i2c_resources[] = {
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};
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static struct platform_device nlm_xlr_i2c_1 = {
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.name = "xlr-i2cbus",
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.id = 1,
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.name = "xlr-i2cbus",
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.id = 1,
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.num_resources = 1,
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.resource = i2c_resources,
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};
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@@ -163,7 +163,7 @@ static void prom_add_memory(void)
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{
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struct nlm_boot_mem_map *bootm;
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u64 start, size;
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u64 pref_backup = 512; /* avoid pref walking beyond end */
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u64 pref_backup = 512; /* avoid pref walking beyond end */
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int i;
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bootm = (void *)(long)nlm_prom_info.psb_mem_map;
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