MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
此提交包含在：
Ralf Baechle
@@ -40,7 +40,7 @@
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#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
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#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
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#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
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#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
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#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
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#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
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#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
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@@ -115,9 +115,9 @@
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#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
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#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
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#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
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#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
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#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
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#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
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#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
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#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
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#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
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#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
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@@ -127,11 +127,11 @@
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#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
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#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
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#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
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#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
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#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
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#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
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#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
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#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
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#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
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#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
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#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
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#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
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#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
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@@ -147,7 +147,7 @@
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#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
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/* Clocks */
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#define JMR3927_CORECLK 132710400 /* 132.7MHz */
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#define JMR3927_CORECLK 132710400 /* 132.7MHz */
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/*
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* TX3927 Pin Configuration:
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@@ -1,6 +1,6 @@
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/*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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* source@mvista.com
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*
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* Copyright 2001-2002 MontaVista Software Inc.
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*
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@@ -38,7 +38,7 @@
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#define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
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#define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
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#define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
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#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
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#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
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#define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
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#define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
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#define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
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@@ -50,7 +50,7 @@
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#define rbtx4927_imask_addr ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
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#define rbtx4927_imstat_addr ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
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#define rbtx4927_softint_addr ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
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#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
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#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
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#define rbtx4927_softresetlock_addr \
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((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
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#define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
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@@ -36,7 +36,7 @@
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#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
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#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
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#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
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#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
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#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
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#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
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#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
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#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
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@@ -78,7 +78,7 @@
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#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
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#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
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#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
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#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
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#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
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#define rbtx4938_softresetlock_addr \
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((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
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#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
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@@ -94,7 +94,7 @@
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/* These are the virtual IRQ numbers, we divide all IRQ's into
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* 'spaces', the 'space' determines where and how to enable/disable
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* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
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* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
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* IRQ hardware is supported.
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*/
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#define RBTX4938_NR_IRQ_IOC 8
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@@ -103,18 +103,18 @@
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#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
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#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
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#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
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#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
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#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
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#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
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#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
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#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
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#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
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#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
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#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
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#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
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#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
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#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
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#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
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#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
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#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
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#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
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#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
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#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
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#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
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#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
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#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
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#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
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@@ -17,7 +17,7 @@
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/* Address map */
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#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
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#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
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#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)
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#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002)
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#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004)
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#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006)
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@@ -46,9 +46,9 @@
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#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c)
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#define RBTX4939_7SEG_ADDR(s, ch) \
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(IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
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#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
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#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)
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#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002)
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#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
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#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)
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#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000)
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/* Ethernet port address */
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@@ -77,11 +77,11 @@
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#define RBTX4939_PE2_CIR 0x08
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#define RBTX4939_PE2_SPI 0x10
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#define RBTX4939_PE2_GPIO 0x20
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#define RBTX4939_PE3_VP 0x01
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#define RBTX4939_PE3_VP 0x01
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#define RBTX4939_PE3_VP_P 0x02
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#define RBTX4939_PE3_VP_S 0x04
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#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
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#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
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#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
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#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
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#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
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@@ -110,9 +110,9 @@
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#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
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#define rbtx4939_7seg_addr(s, ch) \
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((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
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#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
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#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
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#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
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#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
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#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
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/*
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* IRQ mappings
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@@ -18,43 +18,43 @@
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/* Common Registers */
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#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
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#define SMSC_FDC37M81X_CONFIG_DATA 0x01
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#define SMSC_FDC37M81X_CONF 0x02
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#define SMSC_FDC37M81X_INDEX 0x03
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#define SMSC_FDC37M81X_DNUM 0x07
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#define SMSC_FDC37M81X_DID 0x20
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#define SMSC_FDC37M81X_DREV 0x21
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#define SMSC_FDC37M81X_PCNT 0x22
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#define SMSC_FDC37M81X_PMGT 0x23
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#define SMSC_FDC37M81X_OSC 0x24
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#define SMSC_FDC37M81X_CONFPA0 0x26
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#define SMSC_FDC37M81X_CONFPA1 0x27
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#define SMSC_FDC37M81X_TEST4 0x2B
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#define SMSC_FDC37M81X_TEST5 0x2C
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#define SMSC_FDC37M81X_TEST1 0x2D
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#define SMSC_FDC37M81X_TEST2 0x2E
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#define SMSC_FDC37M81X_TEST3 0x2F
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#define SMSC_FDC37M81X_CONF 0x02
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#define SMSC_FDC37M81X_INDEX 0x03
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#define SMSC_FDC37M81X_DNUM 0x07
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#define SMSC_FDC37M81X_DID 0x20
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#define SMSC_FDC37M81X_DREV 0x21
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#define SMSC_FDC37M81X_PCNT 0x22
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#define SMSC_FDC37M81X_PMGT 0x23
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#define SMSC_FDC37M81X_OSC 0x24
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#define SMSC_FDC37M81X_CONFPA0 0x26
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#define SMSC_FDC37M81X_CONFPA1 0x27
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#define SMSC_FDC37M81X_TEST4 0x2B
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#define SMSC_FDC37M81X_TEST5 0x2C
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#define SMSC_FDC37M81X_TEST1 0x2D
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#define SMSC_FDC37M81X_TEST2 0x2E
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#define SMSC_FDC37M81X_TEST3 0x2F
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/* Logical device numbers */
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#define SMSC_FDC37M81X_FDD 0x00
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#define SMSC_FDC37M81X_PARALLEL 0x03
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#define SMSC_FDC37M81X_SERIAL1 0x04
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#define SMSC_FDC37M81X_SERIAL2 0x05
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#define SMSC_FDC37M81X_KBD 0x07
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#define SMSC_FDC37M81X_AUXIO 0x08
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#define SMSC_FDC37M81X_NONE 0xff
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#define SMSC_FDC37M81X_FDD 0x00
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#define SMSC_FDC37M81X_PARALLEL 0x03
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#define SMSC_FDC37M81X_SERIAL1 0x04
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#define SMSC_FDC37M81X_SERIAL2 0x05
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#define SMSC_FDC37M81X_KBD 0x07
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#define SMSC_FDC37M81X_AUXIO 0x08
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#define SMSC_FDC37M81X_NONE 0xff
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/* Logical device Config Registers */
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#define SMSC_FDC37M81X_ACTIVE 0x30
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#define SMSC_FDC37M81X_ACTIVE 0x30
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#define SMSC_FDC37M81X_BASEADDR0 0x60
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#define SMSC_FDC37M81X_BASEADDR1 0x61
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#define SMSC_FDC37M81X_INT 0x70
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#define SMSC_FDC37M81X_INT2 0x72
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#define SMSC_FDC37M81X_LDCR_F0 0xF0
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#define SMSC_FDC37M81X_INT 0x70
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#define SMSC_FDC37M81X_INT2 0x72
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#define SMSC_FDC37M81X_LDCR_F0 0xF0
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/* Chip Config Values */
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#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
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#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
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#define SMSC_FDC37M81X_CHIP_ID 0x4d
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#define SMSC_FDC37M81X_CHIP_ID 0x4d
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unsigned long smsc_fdc37m81x_init(unsigned long port);
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@@ -8,8 +8,8 @@
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#ifndef __ASM_TXX9_TX3927_H
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#define __ASM_TXX9_TX3927_H
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#define TX3927_REG_BASE 0xfffe0000UL
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#define TX3927_REG_SIZE 0x00010000
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#define TX3927_REG_BASE 0xfffe0000UL
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#define TX3927_REG_SIZE 0x00010000
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#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
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#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
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#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
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@@ -191,8 +191,8 @@ struct tx3927_ccfg_reg {
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#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
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#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
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#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
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#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
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#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
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#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
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#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
|
||||
#define TX3927_DMA_CCR_MEMIO 0x00000002
|
||||
#define TX3927_DMA_CCR_ONEAD 0x00000001
|
||||
|
||||
@@ -250,7 +250,7 @@ struct tx3927_ccfg_reg {
|
||||
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
|
||||
|
||||
/* bits for PBAPMC */
|
||||
#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
|
||||
#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
|
||||
#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
|
||||
#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
|
||||
|
||||
@@ -282,7 +282,7 @@ struct tx3927_ccfg_reg {
|
||||
#define TX3927_CCFG_TLBOFF 0x00020000
|
||||
#define TX3927_CCFG_BEOW 0x00010000
|
||||
#define TX3927_CCFG_WR 0x00008000
|
||||
#define TX3927_CCFG_TOE 0x00004000
|
||||
#define TX3927_CCFG_TOE 0x00004000
|
||||
#define TX3927_CCFG_PCIXARB 0x00002000
|
||||
#define TX3927_CCFG_PCI3 0x00001000
|
||||
#define TX3927_CCFG_PSNP 0x00000800
|
||||
@@ -301,8 +301,8 @@ struct tx3927_ccfg_reg {
|
||||
#define TX3927_PCFG_SELALL 0x0003ffff
|
||||
#define TX3927_PCFG_SELCS 0x00020000
|
||||
#define TX3927_PCFG_SELDSF 0x00010000
|
||||
#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
|
||||
#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
|
||||
#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
|
||||
#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
|
||||
#define TX3927_PCFG_SELSIO_ALL 0x00003000
|
||||
#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
|
||||
#define TX3927_PCFG_SELTMR_ALL 0x00000e00
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
* source@mvista.com
|
||||
*
|
||||
* Copyright 2001-2006 MontaVista Software Inc.
|
||||
*
|
||||
@@ -33,11 +33,11 @@
|
||||
#include <asm/txx9/tx4927pcic.h>
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TX4927_REG_BASE 0xffffffffff1f0000UL
|
||||
#define TX4927_REG_BASE 0xffffffffff1f0000UL
|
||||
#else
|
||||
#define TX4927_REG_BASE 0xff1f0000UL
|
||||
#define TX4927_REG_BASE 0xff1f0000UL
|
||||
#endif
|
||||
#define TX4927_REG_SIZE 0x00010000
|
||||
#define TX4927_REG_SIZE 0x00010000
|
||||
|
||||
#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
|
||||
#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
|
||||
@@ -118,10 +118,10 @@ struct tx4927_ccfg_reg {
|
||||
#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
|
||||
#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
|
||||
#define TX4927_CCFG_BEOW 0x00010000
|
||||
#define TX4927_CCFG_WR 0x00008000
|
||||
#define TX4927_CCFG_TOE 0x00004000
|
||||
#define TX4927_CCFG_TOE 0x00004000
|
||||
#define TX4927_CCFG_PCIARB 0x00002000
|
||||
#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
|
||||
#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
|
||||
@@ -136,10 +136,10 @@ struct tx4927_ccfg_reg {
|
||||
|
||||
/* PCFG : Pin Configuration */
|
||||
#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
|
||||
#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4927_PCFG_SYSCLKEN 0x08000000
|
||||
#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
|
||||
#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
#define TX4927_PCFG_SEL2 0x00000200
|
||||
|
||||
@@ -93,7 +93,7 @@ struct tx4927_pcic_reg {
|
||||
|
||||
/* bits for PBACFG */
|
||||
#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
|
||||
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4927_PCIC_PBACFG_RPBA 0x00000004
|
||||
#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
|
||||
#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
|
||||
|
||||
@@ -165,7 +165,7 @@ struct tx4927_pcic_reg {
|
||||
#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
|
||||
#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
|
||||
#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
|
||||
#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
|
||||
@@ -174,7 +174,7 @@ struct tx4927_pcic_reg {
|
||||
|
||||
/* bits for PDMSTS */
|
||||
#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
|
||||
#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
|
||||
#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
|
||||
#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
|
||||
|
||||
@@ -16,11 +16,11 @@
|
||||
#include <asm/txx9/tx4927.h>
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
|
||||
#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
|
||||
#else
|
||||
#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
|
||||
#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
|
||||
#endif
|
||||
#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
|
||||
#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
|
||||
|
||||
/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
|
||||
#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
|
||||
@@ -72,16 +72,16 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_NUM_IR_DMA 4
|
||||
#define TX4938_IR_DMA(ch, n) ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
|
||||
#define TX4938_IR_PIO 14
|
||||
#define TX4938_IR_PDMAC 15
|
||||
#define TX4938_IR_PDMAC 15
|
||||
#define TX4938_IR_PCIC 16
|
||||
#define TX4938_NUM_IR_TMR 3
|
||||
#define TX4938_IR_TMR(n) (17 + (n))
|
||||
#define TX4938_IR_NDFMC 21
|
||||
#define TX4938_IR_NDFMC 21
|
||||
#define TX4938_IR_PCIERR 22
|
||||
#define TX4938_IR_PCIPME 23
|
||||
#define TX4938_IR_ACLC 24
|
||||
#define TX4938_IR_ACLCPME 25
|
||||
#define TX4938_IR_PCIC1 26
|
||||
#define TX4938_IR_PCIC1 26
|
||||
#define TX4938_IR_SPI 31
|
||||
#define TX4938_NUM_IR 32
|
||||
/* multiplex */
|
||||
@@ -105,10 +105,10 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_CCFG_PCI1_66 0x00200000
|
||||
#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
|
||||
#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
|
||||
#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
|
||||
#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
|
||||
#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
|
||||
#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
|
||||
#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
|
||||
#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
|
||||
#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
|
||||
#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
|
||||
#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
|
||||
@@ -116,7 +116,7 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
|
||||
#define TX4938_CCFG_BEOW 0x00010000
|
||||
#define TX4938_CCFG_WR 0x00008000
|
||||
#define TX4938_CCFG_TOE 0x00004000
|
||||
#define TX4938_CCFG_TOE 0x00004000
|
||||
#define TX4938_CCFG_PCIARB 0x00002000
|
||||
#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
|
||||
#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
|
||||
@@ -141,10 +141,10 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
|
||||
#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
|
||||
#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
|
||||
#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
|
||||
#define TX4938_PCFG_SYSCLKEN 0x08000000
|
||||
#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
|
||||
#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
|
||||
#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
|
||||
#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
|
||||
#define TX4938_PCFG_SEL2 0x00000200
|
||||
@@ -230,8 +230,8 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
|
||||
#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
|
||||
#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
|
||||
#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
|
||||
#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
|
||||
#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
|
||||
#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
|
||||
#define TX4938_DMA_CCR_MEMIO 0x00000002
|
||||
#define TX4938_DMA_CCR_SNGAD 0x00000001
|
||||
|
||||
@@ -263,9 +263,9 @@ struct tx4938_ccfg_reg {
|
||||
#define TX4938_REV_PCODE() \
|
||||
((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
|
||||
|
||||
#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
|
||||
#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
|
||||
#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
|
||||
#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
|
||||
#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
|
||||
|
||||
#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
|
||||
#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
#include <asm/txx9/tx4938.h>
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
|
||||
#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */
|
||||
#else
|
||||
#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
|
||||
#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */
|
||||
#endif
|
||||
#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
|
||||
#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */
|
||||
|
||||
#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
|
||||
#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000)
|
||||
@@ -189,14 +189,14 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_IR_INT(n) (3 + (n))
|
||||
#define TX4939_NUM_IR_ETH 2
|
||||
#define TX4939_IR_ETH(n) ((n) ? 43 : 6)
|
||||
#define TX4939_IR_VIDEO 7
|
||||
#define TX4939_IR_VIDEO 7
|
||||
#define TX4939_IR_CIR 8
|
||||
#define TX4939_NUM_IR_SIO 4
|
||||
#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */
|
||||
#define TX4939_NUM_IR_DMA 4
|
||||
#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
|
||||
#define TX4939_IR_IRC 14
|
||||
#define TX4939_IR_PDMAC 15
|
||||
#define TX4939_IR_PDMAC 15
|
||||
#define TX4939_NUM_IR_TMR 6
|
||||
#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
|
||||
#define TX4939_NUM_IR_ATA 2
|
||||
@@ -210,10 +210,10 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_IR_I2C 33
|
||||
#define TX4939_IR_SPI 34
|
||||
#define TX4939_IR_PCIC 35
|
||||
#define TX4939_IR_PCIC1 36
|
||||
#define TX4939_IR_PCIC1 36
|
||||
#define TX4939_IR_PCIERR 37
|
||||
#define TX4939_IR_PCIPME 38
|
||||
#define TX4939_IR_NDFMC 39
|
||||
#define TX4939_IR_NDFMC 39
|
||||
#define TX4939_IR_ACLCPME 40
|
||||
#define TX4939_IR_RTC 41
|
||||
#define TX4939_IR_RND 42
|
||||
@@ -239,7 +239,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_CCFG_PCI66 0x00800000
|
||||
#define TX4939_CCFG_PCIMODE 0x00400000
|
||||
#define TX4939_CCFG_SSCG 0x00100000
|
||||
#define TX4939_CCFG_MULCLK_MASK 0x000e0000
|
||||
#define TX4939_CCFG_MULCLK_MASK 0x000e0000
|
||||
#define TX4939_CCFG_MULCLK_8 (0x7 << 17)
|
||||
#define TX4939_CCFG_MULCLK_9 (0x0 << 17)
|
||||
#define TX4939_CCFG_MULCLK_10 (0x1 << 17)
|
||||
@@ -250,7 +250,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_CCFG_MULCLK_15 (0x6 << 17)
|
||||
#define TX4939_CCFG_BEOW 0x00010000
|
||||
#define TX4939_CCFG_WR 0x00008000
|
||||
#define TX4939_CCFG_TOE 0x00004000
|
||||
#define TX4939_CCFG_TOE 0x00004000
|
||||
#define TX4939_CCFG_PCIARB 0x00002000
|
||||
#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00
|
||||
#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
|
||||
@@ -275,7 +275,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL
|
||||
#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL
|
||||
#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL
|
||||
@@ -392,15 +392,15 @@ struct tx4939_vpc_desc {
|
||||
/*
|
||||
* CRYPTO
|
||||
*/
|
||||
#define TX4939_CRYPTO_CSR_SAESO 0x08000000
|
||||
#define TX4939_CRYPTO_CSR_SAESI 0x04000000
|
||||
#define TX4939_CRYPTO_CSR_SDESO 0x02000000
|
||||
#define TX4939_CRYPTO_CSR_SDESI 0x01000000
|
||||
#define TX4939_CRYPTO_CSR_SAESO 0x08000000
|
||||
#define TX4939_CRYPTO_CSR_SAESI 0x04000000
|
||||
#define TX4939_CRYPTO_CSR_SDESO 0x02000000
|
||||
#define TX4939_CRYPTO_CSR_SDESI 0x01000000
|
||||
#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
|
||||
#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20)
|
||||
#define TX4939_CRYPTO_CSR_TOINT 0x00080000
|
||||
#define TX4939_CRYPTO_CSR_DCINT 0x00040000
|
||||
#define TX4939_CRYPTO_CSR_GBINT 0x00010000
|
||||
#define TX4939_CRYPTO_CSR_TOINT 0x00080000
|
||||
#define TX4939_CRYPTO_CSR_DCINT 0x00040000
|
||||
#define TX4939_CRYPTO_CSR_GBINT 0x00010000
|
||||
#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
|
||||
#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13)
|
||||
#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800
|
||||
@@ -418,7 +418,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040
|
||||
#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080
|
||||
#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0
|
||||
#define TX4939_CRYPTO_CSR_GINTE 0x00000008
|
||||
#define TX4939_CRYPTO_CSR_GINTE 0x00000008
|
||||
#define TX4939_CRYPTO_CSR_RSTD 0x00000004
|
||||
#define TX4939_CRYPTO_CSR_RSTC 0x00000002
|
||||
#define TX4939_CRYPTO_CSR_ENCR 0x00000001
|
||||
@@ -442,7 +442,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_CRYPTO_DESC_START 0x00000200
|
||||
#define TX4939_CRYPTO_DESC_END 0x00000100
|
||||
#define TX4939_CRYPTO_DESC_XOR 0x00000010
|
||||
#define TX4939_CRYPTO_DESC_LAST 0x00000008
|
||||
#define TX4939_CRYPTO_DESC_LAST 0x00000008
|
||||
#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006
|
||||
#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000
|
||||
#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002
|
||||
@@ -457,7 +457,7 @@ struct tx4939_vpc_desc {
|
||||
|
||||
#define TX4939_CRYPTO_NR_SET 6
|
||||
|
||||
#define TX4939_CRYPTO_RCSR_INTE 0x00000008
|
||||
#define TX4939_CRYPTO_RCSR_INTE 0x00000008
|
||||
#define TX4939_CRYPTO_RCSR_RST 0x00000004
|
||||
#define TX4939_CRYPTO_RCSR_FIN 0x00000002
|
||||
#define TX4939_CRYPTO_RCSR_ST 0x00000001
|
||||
@@ -480,8 +480,8 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000
|
||||
#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010
|
||||
#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030
|
||||
#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
|
||||
#define TX4939_VPC_CTRLA_VDMODE 0x00000004
|
||||
#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
|
||||
#define TX4939_VPC_CTRLA_VDMODE 0x00000004
|
||||
#define TX4939_VPC_CTRLA_VDFOR 0x00000002
|
||||
#define TX4939_VPC_CTRLA_ENVPC 0x00000001
|
||||
|
||||
@@ -512,9 +512,9 @@ struct tx4939_vpc_desc {
|
||||
((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
|
||||
>> 32))
|
||||
|
||||
#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
|
||||
#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)
|
||||
#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits)
|
||||
#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
|
||||
#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)
|
||||
|
||||
#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
|
||||
#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
|
||||
@@ -522,7 +522,7 @@ struct tx4939_vpc_desc {
|
||||
#define TX4939_EBUSC_WIDTH(ch) \
|
||||
(16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
|
||||
|
||||
/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
|
||||
/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */
|
||||
#define TX4939_SCLK0(mst) \
|
||||
((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
|
||||
|
||||
|
||||
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