amd-xgbe: Adjust register settings to improve performance
Add support to change some general performance settings and to provide some performance settings based on the device that is probed. This includes: - Setting the maximum read/write outstanding request limit - Reducing the AXI interface burst length size - Selectively setting the Tx and Rx descriptor pre-fetch threshold - Selectively setting additional cache coherency controls Tested and verified on all versions of the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller

parent
7e1e6b86a5
commit
6f595959c0
@@ -2114,18 +2114,38 @@ static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
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static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
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{
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unsigned int sbmr;
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sbmr = XGMAC_IOREAD(pdata, DMA_SBMR);
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/* Set enhanced addressing mode */
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XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);
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/* Set the System Bus mode */
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XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
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XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN, pdata->blen >> 2);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
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XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
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XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr);
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/* Set descriptor fetching threshold */
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if (pdata->vdata->tx_desc_prefetch)
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XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS,
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pdata->vdata->tx_desc_prefetch);
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if (pdata->vdata->rx_desc_prefetch)
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XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS,
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pdata->vdata->rx_desc_prefetch);
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}
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static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
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{
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XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr);
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XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr);
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if (pdata->awarcr)
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XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr);
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}
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static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
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