rt2x00: Add/Modify protection related register definitions
Make the definition of protection related registers more precisely Signed-off-by: Shiang Tu <shiang_tu@ralinktech.com> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville

parent
47715e6473
commit
6f492b6d38
@@ -1138,8 +1138,8 @@
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* PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
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* PROTECT_CTRL: Protection control frame type for CCK TX
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* 0:none, 1:RTS/CTS, 2:CTS-to-self
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* PROTECT_NAV: TXOP protection type for CCK TX
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* 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
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* PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
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* PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
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* TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
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* TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
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* TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
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@@ -1151,7 +1151,8 @@
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#define CCK_PROT_CFG 0x1364
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#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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@@ -1166,7 +1167,8 @@
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#define OFDM_PROT_CFG 0x1368
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#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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@@ -1181,7 +1183,8 @@
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#define MM20_PROT_CFG 0x136c
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#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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@@ -1196,7 +1199,8 @@
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#define MM40_PROT_CFG 0x1370
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#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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@@ -1211,7 +1215,8 @@
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#define GF20_PROT_CFG 0x1374
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#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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@@ -1226,7 +1231,8 @@
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#define GF40_PROT_CFG 0x1378
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#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
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#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
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#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
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#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
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#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
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#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
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#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
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#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
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