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ANDROID: coresight: Update ETE/TRBE to v6 merged upstream

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Mark the buffer as truncated in irq + minor cleanups picked along the
way.

Bug: 174685394
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
Change-Id: I36111a14ef066b579a28c39e265f3d601a82e18a
This commit is contained in:
Qais Yousef
2021-04-26 12:21:58 +01:00
committed by Todd Kjos
parent ce71010347
commit 6f1bd7583f
4 changed files with 17 additions and 10 deletions
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2
drivers/hwtracing/coresight/coresight-core.c
View File

@@ -23,7 +23,7 @@
#include "coresight-priv.h"
static DEFINE_MUTEX(coresight_mutex);
DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
/**
* struct coresight_node - elements of a path, from source to sink

4
drivers/hwtracing/coresight/coresight-etm4x-core.c
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@@ -115,7 +115,7 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
}
}
u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
{
u64 res = 0;
@@ -132,7 +132,7 @@ u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
return res;
}
void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
{
if (!_relaxed)
__iowmb(); /* Imitate the !relaxed I/O helpers */

18
drivers/hwtracing/coresight/coresight-trbe.c
View File

@@ -5,6 +5,8 @@
* device (ETE) thus generating required trace data. Trace can be enabled
* via the perf framework.
*
* The AUX buffer handling is inspired from Arm SPE PMU driver.
*
* Copyright (C) 2020 ARM Ltd.
*
* Author: Anshuman Khandual <anshuman.khandual@arm.com>
@@ -515,7 +517,7 @@ static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
if (!buf->trbe_base) {
kfree(pglist);
kfree(buf);
return ERR_PTR(buf->trbe_base);
return ERR_PTR(-ENOMEM);
}
buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE;
buf->trbe_write = buf->trbe_base;
@@ -614,9 +616,10 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
/*
* Otherwise, the buffer is full and the write pointer
* has reached base. Adjust this back to the Limit pointer
* for correct size.
* for correct size. Also, mark the buffer truncated.
*/
write = get_trbe_limit_pointer();
perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
}
offset = write - base;
@@ -703,7 +706,12 @@ static void trbe_handle_overflow(struct perf_output_handle *handle)
if (buf->snapshot)
handle->head += size;
perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW);
/*
* Mark the buffer as truncated, as we have stopped the trace
* collection upon the WRAP event, without stopping the source.
*/
perf_aux_output_flag(handle, PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW |
PERF_AUX_FLAG_TRUNCATED);
perf_aux_output_end(handle, size);
event_data = perf_aux_output_begin(handle, event);
if (!event_data) {
@@ -863,7 +871,7 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp
dev = &cpudata->drvdata->pdev->dev;
desc.name = devm_kasprintf(dev, GFP_KERNEL, "trbe%d", cpu);
if (IS_ERR(desc.name))
if (!desc.name)
goto cpu_clear;
desc.type = CORESIGHT_DEV_TYPE_SINK;
@@ -1038,7 +1046,7 @@ static int arm_trbe_probe_irq(struct platform_device *pdev,
if (irq_get_percpu_devid_partition(drvdata->irq, &drvdata->supported_cpus))
return -EINVAL;
drvdata->handle = alloc_percpu(typeof(*drvdata->handle));
drvdata->handle = alloc_percpu(struct perf_output_handle *);
if (!drvdata->handle)
return -ENOMEM;

3
drivers/hwtracing/coresight/coresight-trbe.h
View File

@@ -128,8 +128,7 @@ static inline void set_trbe_write_pointer(unsigned long addr)
static inline unsigned long get_trbe_limit_pointer(void)
{
u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
unsigned long limit = (trblimitr >> TRBLIMITR_LIMIT_SHIFT) & TRBLIMITR_LIMIT_MASK;
unsigned long addr = limit << TRBLIMITR_LIMIT_SHIFT;
unsigned long addr = trblimitr & (TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
return addr;