xen: support 52 bit physical addresses in pv guests
Physical addresses on processors supporting 5 level paging can be up to 52 bits wide. For a Xen pv guest running on such a machine those physical addresses have to be supported in order to be able to use any memory on the machine even if the guest itself does not support 5 level paging. So when reading/writing a MFN from/to a pte don't use the kernel's PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs. Signed-off-by: Juergen Gross <jgross@suse.com> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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committed by
Boris Ostrovsky

parent
5eee149ab9
commit
6f0e8bf167
@@ -26,6 +26,15 @@ typedef struct xpaddr {
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phys_addr_t paddr;
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} xpaddr_t;
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#ifdef CONFIG_X86_64
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#define XEN_PHYSICAL_MASK __sme_clr((1UL << 52) - 1)
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#else
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#define XEN_PHYSICAL_MASK __PHYSICAL_MASK
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#endif
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#define XEN_PTE_MFN_MASK ((pteval_t)(((signed long)PAGE_MASK) & \
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XEN_PHYSICAL_MASK))
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#define XMADDR(x) ((xmaddr_t) { .maddr = (x) })
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#define XPADDR(x) ((xpaddr_t) { .paddr = (x) })
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@@ -277,7 +286,7 @@ static inline unsigned long bfn_to_local_pfn(unsigned long mfn)
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static inline unsigned long pte_mfn(pte_t pte)
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{
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return (pte.pte & PTE_PFN_MASK) >> PAGE_SHIFT;
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return (pte.pte & XEN_PTE_MFN_MASK) >> PAGE_SHIFT;
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}
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static inline pte_t mfn_pte(unsigned long page_nr, pgprot_t pgprot)
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