ARM: imx5: add step clock, used when reprogramming PLL1
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
@@ -198,6 +198,8 @@
|
||||
#define IMX5_CLK_OCRAM 186
|
||||
#define IMX5_CLK_SAHARA_IPG_GATE 187
|
||||
#define IMX5_CLK_SATA_REF 188
|
||||
#define IMX5_CLK_END 189
|
||||
#define IMX5_CLK_STEP_SEL 189
|
||||
#define IMX5_CLK_CPU_PODF_SEL 190
|
||||
#define IMX5_CLK_END 191
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
|
||||
|
Reference in New Issue
Block a user