ath9k_hw: Fix low throughput issue with AR93xx
TX underruns were noticed when RTS/CTS preceded aggregates. This issue was noticed in ar93xx family of chipsets only. The workaround involves padding the RTS or CTS length up to the min packet length of 256 bytes required by the hardware by adding delimiters to the fist descriptor of the aggregate. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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John W. Linville

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@@ -803,6 +803,9 @@ struct ath_hw {
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* this register when in sleep states.
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*/
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u32 WARegVal;
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/* Enterprise mode cap */
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u32 ent_mode;
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};
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static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
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