ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
@@ -69,7 +69,7 @@ ENTRY(cpu_feroceon_proc_init)
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movne r2, r2, lsr #2 @ turned into # of sets
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sub r2, r2, #(1 << 5)
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stmia r1, {r2, r3}
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mov pc, lr
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ret lr
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/*
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* cpu_feroceon_proc_fin()
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@@ -86,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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ret lr
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/*
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* cpu_feroceon_reset(loc)
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@@ -110,7 +110,7 @@ ENTRY(cpu_feroceon_reset)
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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ret r0
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ENDPROC(cpu_feroceon_reset)
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.popsection
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@@ -124,7 +124,7 @@ ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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ret lr
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/*
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* flush_icache_all()
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@@ -134,7 +134,7 @@ ENTRY(cpu_feroceon_do_idle)
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ENTRY(feroceon_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mov pc, lr
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ret lr
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ENDPROC(feroceon_flush_icache_all)
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/*
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@@ -169,7 +169,7 @@ __flush_whole_cache:
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mov ip, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/*
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* flush_user_cache_range(start, end, flags)
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@@ -198,7 +198,7 @@ ENTRY(feroceon_flush_user_cache_range)
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/*
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* coherent_kern_range(start, end)
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@@ -233,7 +233,7 @@ ENTRY(feroceon_coherent_user_range)
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov r0, #0
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mov pc, lr
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ret lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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@@ -254,7 +254,7 @@ ENTRY(feroceon_flush_kern_dcache_area)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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.align 5
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ENTRY(feroceon_range_flush_kern_dcache_area)
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@@ -268,7 +268,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/*
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* dma_inv_range(start, end)
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@@ -295,7 +295,7 @@ feroceon_dma_inv_range:
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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.align 5
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feroceon_range_dma_inv_range:
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@@ -311,7 +311,7 @@ feroceon_range_dma_inv_range:
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mcr p15, 5, r0, c15, c14, 0 @ D inv range start
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mcr p15, 5, r1, c15, c14, 1 @ D inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov pc, lr
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ret lr
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/*
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* dma_clean_range(start, end)
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@@ -331,7 +331,7 @@ feroceon_dma_clean_range:
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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.align 5
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feroceon_range_dma_clean_range:
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@@ -344,7 +344,7 @@ feroceon_range_dma_clean_range:
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mcr p15, 5, r1, c15, c13, 1 @ D clean range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/*
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* dma_flush_range(start, end)
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@@ -362,7 +362,7 @@ ENTRY(feroceon_dma_flush_range)
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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.align 5
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ENTRY(feroceon_range_dma_flush_range)
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@@ -375,7 +375,7 @@ ENTRY(feroceon_range_dma_flush_range)
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/*
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* dma_map_area(start, size, dir)
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@@ -412,7 +412,7 @@ ENDPROC(feroceon_range_dma_map_area)
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* - dir - DMA direction
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*/
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ENTRY(feroceon_dma_unmap_area)
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mov pc, lr
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ret lr
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ENDPROC(feroceon_dma_unmap_area)
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.globl feroceon_flush_kern_cache_louis
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@@ -461,7 +461,7 @@ ENTRY(cpu_feroceon_dcache_clean_area)
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bhi 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ret lr
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/* =============================== PageTable ============================== */
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@@ -490,9 +490,9 @@ ENTRY(cpu_feroceon_switch_mm)
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, r2
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ret r2
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#else
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mov pc, lr
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ret lr
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#endif
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/*
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@@ -512,7 +512,7 @@ ENTRY(cpu_feroceon_set_pte_ext)
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mov pc, lr
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ret lr
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/* Suspend/resume support: taken from arch/arm/mm/proc-arm926.S */
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.globl cpu_feroceon_suspend_size
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@@ -554,7 +554,7 @@ __feroceon_setup:
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mrc p15, 0, r0, c1, c0 @ get control register v4
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bic r0, r0, r5
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orr r0, r0, r6
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mov pc, lr
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ret lr
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.size __feroceon_setup, . - __feroceon_setup
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/*
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