ASoC: SOF: Intel: Add Intel specific HDA IPC mechanisms.
Add HDA specific IPC mechanism for Intel DSP HW. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com> Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Mark Brown <broonie@kernel.org>
Dieser Commit ist enthalten in:
Liam Girdwood
committet von
Mark Brown
Mark Brown
Ursprung
747503b181
Commit
6e9cde9748
458
sound/soc/sof/intel/hda-ipc.c
Normale Datei
458
sound/soc/sof/intel/hda-ipc.c
Normale Datei
@@ -0,0 +1,458 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2018 Intel Corporation. All rights reserved.
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//
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// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
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// Rander Wang <rander.wang@intel.com>
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// Keyon Jie <yang.jie@linux.intel.com>
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//
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/*
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* Hardware interface for generic Intel audio DSP HDA IP
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*/
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#include "../ops.h"
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#include "hda.h"
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static void hda_dsp_ipc_host_done(struct snd_sof_dev *sdev)
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{
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/*
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* tell DSP cmd is done - clear busy
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* interrupt and send reply msg to dsp
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCT,
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HDA_DSP_REG_HIPCT_BUSY,
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HDA_DSP_REG_HIPCT_BUSY);
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/* unmask BUSY interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_BUSY,
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HDA_DSP_REG_HIPCCTL_BUSY);
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}
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static void hda_dsp_ipc_dsp_done(struct snd_sof_dev *sdev)
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{
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/*
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* set DONE bit - tell DSP we have received the reply msg
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* from DSP, and processed it, don't send more reply to host
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*/
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCIE,
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HDA_DSP_REG_HIPCIE_DONE,
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HDA_DSP_REG_HIPCIE_DONE);
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/* unmask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_DONE,
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HDA_DSP_REG_HIPCCTL_DONE);
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}
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int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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u32 cmd = msg->header;
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/* send IPC message to DSP */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI,
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cmd | HDA_DSP_REG_HIPCI_BUSY);
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return 0;
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}
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void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev)
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{
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struct snd_sof_ipc_msg *msg = sdev->msg;
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struct sof_ipc_reply reply;
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struct sof_ipc_cmd_hdr *hdr;
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unsigned long flags;
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int ret = 0;
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/*
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* Sometimes, there is unexpected reply ipc arriving. The reply
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* ipc belongs to none of the ipcs sent from driver.
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* In this case, the driver must ignore the ipc.
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*/
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if (!msg) {
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dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
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return;
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}
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spin_lock_irqsave(&sdev->ipc_lock, flags);
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hdr = msg->msg_data;
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if (hdr->cmd == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CTX_SAVE)) {
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/*
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* memory windows are powered off before sending IPC reply,
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* so we can't read the mailbox for CTX_SAVE reply.
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*/
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reply.error = 0;
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reply.hdr.cmd = SOF_IPC_GLB_REPLY;
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reply.hdr.size = sizeof(reply);
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memcpy(msg->reply_data, &reply, sizeof(reply));
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goto out;
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}
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/* get IPC reply from DSP in the mailbox */
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sof_mailbox_read(sdev, sdev->host_box.offset, &reply,
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sizeof(reply));
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if (reply.error < 0) {
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memcpy(msg->reply_data, &reply, sizeof(reply));
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ret = reply.error;
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} else {
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/* reply correct size ? */
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if (reply.hdr.size != msg->reply_size) {
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dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
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msg->reply_size, reply.hdr.size);
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ret = -EINVAL;
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}
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/* read the message */
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if (msg->reply_size > 0)
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sof_mailbox_read(sdev, sdev->host_box.offset,
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msg->reply_data, msg->reply_size);
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}
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out:
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msg->reply_error = ret;
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spin_unlock_irqrestore(&sdev->ipc_lock, flags);
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}
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static bool hda_dsp_ipc_is_sof(uint32_t msg)
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{
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return (msg & (HDA_DSP_IPC_PURGE_FW | 0xf << 9)) != msg ||
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(msg & HDA_DSP_IPC_PURGE_FW) != HDA_DSP_IPC_PURGE_FW;
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}
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/* IPC handler thread */
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irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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irqreturn_t ret = IRQ_NONE;
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u32 hipci;
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u32 hipcie;
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u32 hipct;
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u32 hipcte;
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u32 hipcctl;
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u32 msg;
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u32 msg_ext;
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/* here we handle IPC interrupts only */
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if (!(sdev->irq_status & HDA_DSP_ADSPIS_IPC))
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return IRQ_NONE;
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/* read IPC status */
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hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCIE);
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hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
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hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
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/* reenable IPC interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
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HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
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/* is this a reply message from the DSP */
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if (hipcie & HDA_DSP_REG_HIPCIE_DONE &&
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hipcctl & HDA_DSP_REG_HIPCCTL_DONE) {
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hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCI);
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msg = hipci & HDA_DSP_REG_HIPCI_MSG_MASK;
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msg_ext = hipcie & HDA_DSP_REG_HIPCIE_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* mask Done interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_DONE, 0);
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/* handle immediate reply from DSP core - ignore ROM messages */
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if (hda_dsp_ipc_is_sof(msg)) {
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hda_dsp_ipc_get_reply(sdev);
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snd_sof_ipc_reply(sdev, msg);
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}
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/* wake up sleeper if we are loading code */
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if (sdev->code_loading) {
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sdev->code_loading = 0;
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wake_up(&sdev->waitq);
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}
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/* set the done bit */
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hda_dsp_ipc_dsp_done(sdev);
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ret = IRQ_HANDLED;
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}
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/* is this a new message from DSP */
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if (hipct & HDA_DSP_REG_HIPCT_BUSY &&
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hipcctl & HDA_DSP_REG_HIPCCTL_BUSY) {
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hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCTE);
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msg = hipct & HDA_DSP_REG_HIPCT_MSG_MASK;
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msg_ext = hipcte & HDA_DSP_REG_HIPCTE_MSG_MASK;
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dev_vdbg(sdev->dev,
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"ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
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msg, msg_ext);
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/* mask BUSY interrupt */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_HIPCCTL,
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HDA_DSP_REG_HIPCCTL_BUSY, 0);
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/* handle messages from DSP */
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if ((hipct & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
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/* this is a PANIC message !! */
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snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
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} else {
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/* normal message - process normally */
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snd_sof_ipc_msgs_rx(sdev);
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}
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hda_dsp_ipc_host_done(sdev);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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/* is this IRQ for ADSP ? - we only care about IPC here */
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irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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int ret = IRQ_NONE;
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spin_lock(&sdev->hw_lock);
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/* store status */
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sdev->irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPIS);
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/* invalid message ? */
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if (sdev->irq_status == 0xffffffff)
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goto out;
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/* IPC message ? */
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if (sdev->irq_status & HDA_DSP_ADSPIS_IPC) {
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/* disable IPC interrupt */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
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HDA_DSP_REG_ADSPIC,
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HDA_DSP_ADSPIC_IPC, 0);
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ret = IRQ_WAKE_THREAD;
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}
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out:
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spin_unlock(&sdev->hw_lock);
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return ret;
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}
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/* IPC Firmware ready */
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static void ipc_get_windows(struct snd_sof_dev *sdev)
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{
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struct sof_ipc_window_elem *elem;
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u32 outbox_offset = 0;
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u32 stream_offset = 0;
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u32 inbox_offset = 0;
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u32 outbox_size = 0;
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u32 stream_size = 0;
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u32 inbox_size = 0;
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int i;
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if (!sdev->info_window) {
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dev_err(sdev->dev, "error: have no window info\n");
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return;
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}
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for (i = 0; i < sdev->info_window->num_windows; i++) {
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elem = &sdev->info_window->window[i];
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switch (elem->type) {
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case SOF_IPC_REGION_UPBOX:
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inbox_offset =
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elem->offset + SRAM_WINDOW_OFFSET(elem->id);
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inbox_size = elem->size;
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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inbox_offset,
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elem->size, "inbox",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_DOWNBOX:
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outbox_offset =
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elem->offset + SRAM_WINDOW_OFFSET(elem->id);
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outbox_size = elem->size;
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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outbox_offset,
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elem->size, "outbox",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_TRACE:
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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elem->offset +
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SRAM_WINDOW_OFFSET
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(elem->id),
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elem->size, "etrace",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_DEBUG:
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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elem->offset +
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SRAM_WINDOW_OFFSET
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(elem->id),
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elem->size, "debug",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_STREAM:
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stream_offset =
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elem->offset + SRAM_WINDOW_OFFSET(elem->id);
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stream_size = elem->size;
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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elem->offset +
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SRAM_WINDOW_OFFSET
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(elem->id),
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elem->size, "stream",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_REGS:
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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elem->offset +
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SRAM_WINDOW_OFFSET
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(elem->id),
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elem->size, "regs",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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case SOF_IPC_REGION_EXCEPTION:
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sdev->dsp_oops_offset = elem->offset +
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SRAM_WINDOW_OFFSET(elem->id);
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snd_sof_debugfs_io_item(sdev,
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sdev->bar[HDA_DSP_BAR] +
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elem->offset +
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SRAM_WINDOW_OFFSET
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(elem->id),
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elem->size, "exception",
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SOF_DEBUGFS_ACCESS_D0_ONLY);
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break;
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default:
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dev_err(sdev->dev, "error: get illegal window info\n");
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return;
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}
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}
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if (outbox_size == 0 || inbox_size == 0) {
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dev_err(sdev->dev, "error: get illegal mailbox window\n");
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return;
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}
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snd_sof_dsp_mailbox_init(sdev, inbox_offset, inbox_size,
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outbox_offset, outbox_size);
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sdev->stream_box.offset = stream_offset;
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sdev->stream_box.size = stream_size;
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dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
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inbox_offset, inbox_size);
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dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
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outbox_offset, outbox_size);
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dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
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stream_offset, stream_size);
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}
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/* check for ABI compatibility and create memory windows on first boot */
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int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id)
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{
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struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
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u32 offset;
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int ret;
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/* mailbox must be on 4k boundary */
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offset = HDA_DSP_MBOX_UPLINK_OFFSET;
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dev_dbg(sdev->dev, "ipc: DSP is ready 0x%8.8x offset 0x%x\n",
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msg_id, offset);
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/* no need to re-check version/ABI for subsequent boots */
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if (!sdev->first_boot)
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return 0;
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/* copy data from the DSP FW ready offset */
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sof_block_read(sdev, sdev->mmio_bar, offset, fw_ready,
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sizeof(*fw_ready));
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|
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/* make sure ABI version is compatible */
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ret = snd_sof_ipc_valid(sdev);
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if (ret < 0)
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return ret;
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|
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/* now check for extended data */
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snd_sof_fw_parse_ext_data(sdev, sdev->mmio_bar,
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HDA_DSP_MBOX_UPLINK_OFFSET +
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sizeof(struct sof_ipc_fw_ready));
|
||||
|
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ipc_get_windows(sdev);
|
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|
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return 0;
|
||||
}
|
||||
|
||||
void hda_ipc_msg_data(struct snd_sof_dev *sdev,
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struct snd_pcm_substream *substream,
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void *p, size_t sz)
|
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{
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if (!substream || !sdev->stream_box.size) {
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sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz);
|
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} else {
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struct hdac_stream *hstream = substream->runtime->private_data;
|
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struct sof_intel_hda_stream *hda_stream;
|
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|
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hda_stream = container_of(hstream,
|
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struct sof_intel_hda_stream,
|
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hda_stream.hstream);
|
||||
|
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/* The stream might already be closed */
|
||||
if (hstream)
|
||||
sof_mailbox_read(sdev, hda_stream->stream.posn_offset,
|
||||
p, sz);
|
||||
}
|
||||
}
|
||||
|
||||
int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
|
||||
struct snd_pcm_substream *substream,
|
||||
const struct sof_ipc_pcm_params_reply *reply)
|
||||
{
|
||||
struct hdac_stream *hstream = substream->runtime->private_data;
|
||||
struct sof_intel_hda_stream *hda_stream;
|
||||
/* validate offset */
|
||||
size_t posn_offset = reply->posn_offset;
|
||||
|
||||
hda_stream = container_of(hstream, struct sof_intel_hda_stream,
|
||||
hda_stream.hstream);
|
||||
|
||||
/* check for unaligned offset or overflow */
|
||||
if (posn_offset > sdev->stream_box.size ||
|
||||
posn_offset % sizeof(struct sof_ipc_stream_posn) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
hda_stream->stream.posn_offset = sdev->stream_box.offset + posn_offset;
|
||||
|
||||
dev_dbg(sdev->dev, "pcm: stream dir %d, posn mailbox offset is %zu",
|
||||
substream->stream, hda_stream->stream.posn_offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
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