Merge tag 'nand/for-4.18' of git://git.infradead.org/linux-mtd into mtd/next

Core changes:
- Add Miquel as a NAND maintainer
- Add access mode to the nand_page_io_req struct
- Fix kernel-doc in rawnand.h
- Support bit-wise majority to recover from corrupted ONFI parameter
  pages
- Stop checking FAIL bit after a SET_FEATURES, as documented in the
  ONFI spec

Raw NAND Driver changes:
- Fix and cleanup the error path of many NAND controller drivers
- GPMI:
  * Cleanup/simplification of a few aspects in the driver
  * Take ECC setup specified in the DT into account
- sunxi: remove support for GPIO-based R/B polling
- MTK:
  * Use of_device_get_match_data() instead of of_match_device()
  * Add an entry in MAINTAINERS for this driver
  * Fix nand-ecc-step-size and nand-ecc-strength description in the DT
    bindings doc
- fsl_ifc: fix ->cmdfunc() to read more than one ONFI parameter page

OneNAND driver changes:
- samsung: use dev_get_drvdata() instead of platform_get_drvdata()
This commit is contained in:
Boris Brezillon
2018-06-07 22:52:56 +02:00
22 changed files with 329 additions and 417 deletions

View File

@@ -47,6 +47,11 @@ Optional properties:
partitions written from Linux with this feature
turned on may not be accessible by the BootROM
code.
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step. Needs to be a multiple of 2.
- nand-ecc-step-size: integer representing the number of data bytes
that are covered by a single ECC step. The driver
supports 512 and 1024.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

View File

@@ -50,14 +50,19 @@ Optional:
- nand-on-flash-bbt: Store BBT on NAND Flash.
- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
valid values: 512 and 1024.
valid values:
512 and 1024 on mt2701 and mt2712.
512 only on mt7622.
1024 is recommended for large page NANDs.
- nand-ecc-strength: Number of bits to correct per ECC step.
The valid values that the controller supports are: 4, 6,
8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
48, 52, 56, 60.
The valid values that each controller supports:
mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
32, 36, 40, 44, 48, 52, 56, 60.
mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
mt7622: 4, 6, 8, 10, 12, 14, 16.
The strength should be calculated as follows:
E = (S - F) * 8 / 14
E = (S - F) * 8 / B
S = O / (P / Q)
E : nand-ecc-strength.
S : spare size per sector.
@@ -66,6 +71,15 @@ Optional:
O : oob size.
P : page size.
Q : nand-ecc-step-size.
B : number of parity bits needed to correct
1 bitflip.
According to MTK NAND controller design,
this number depends on max ecc step size
that MTK NAND controller supports.
If max ecc step size supported is 1024,
then it should be always 14. And if max
ecc step size is 512, then it should be
always 13.
If the result does not match any one of the listed
choices above, please select the smaller valid value from
the list.

View File

@@ -22,8 +22,6 @@ Optional properties:
- reset : phandle + reset specifier pair
- reset-names : must contain "ahb"
- allwinner,rb : shall contain the native Ready/Busy ids.
or
- rb-gpios : shall contain the gpios used as R/B pins.
- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
"none")