Merge branch 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM updates (part two) from Russell King: - breakpoint and perf updates from Will Deacon. - hypervisor boot mode updates from Will. - support for Power State Coordination Interface via the Hypervisor - core ARM support for KVM * 'for-linus-2' of git://git.linaro.org/people/rmk/linux-arm: (32 commits) KVM: ARM: Add maintainer entry for KVM/ARM KVM: ARM: Power State Coordination Interface implementation KVM: ARM: Handle I/O aborts KVM: ARM: Handle guest faults in KVM KVM: ARM: VFP userspace interface KVM: ARM: Demux CCSIDR in the userspace API KVM: ARM: User space API for getting/setting co-proc registers KVM: ARM: Emulation framework and CP15 emulation KVM: ARM: World-switch implementation KVM: ARM: Inject IRQs and FIQs from userspace KVM: ARM: Memory virtualization setup KVM: ARM: Hypervisor initialization KVM: ARM: Initial skeleton to compile KVM support ARM: Section based HYP idmap ARM: Add page table and page defines needed by KVM ARM: perf: simplify __hw_perf_event_init err handling ARM: perf: remove unnecessary checks for idx < 0 ARM: perf: handle armpmu_register failing ARM: perf: don't pretend to support counting of L1I writes ARM: perf: remove redundant NULL check on cpu_pmu ...
This commit is contained in:
Linus Torvalds
55
Documentation/devicetree/bindings/arm/psci.txt
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55
Documentation/devicetree/bindings/arm/psci.txt
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@@ -0,0 +1,55 @@
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* Power State Coordination Interface (PSCI)
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Firmware implementing the PSCI functions described in ARM document number
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ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
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processors") can be used by Linux to initiate various CPU-centric power
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operations.
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Issue A of the specification describes functions for CPU suspend, hotplug
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and migration of secure software.
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Functions are invoked by trapping to the privilege level of the PSCI
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firmware (specified as part of the binding below) and passing arguments
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in a manner similar to that specified by AAPCS:
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r0 => 32-bit Function ID / return value
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{r1 - r3} => Parameters
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Note that the immediate field of the trapping instruction must be set
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to #0.
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Main node required properties:
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- compatible : Must be "arm,psci"
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- method : The method of calling the PSCI firmware. Permitted
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values are:
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"smc" : SMC #0, with the register assignments specified
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in this binding.
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"hvc" : HVC #0, with the register assignments specified
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in this binding.
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Main node optional properties:
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- cpu_suspend : Function ID for CPU_SUSPEND operation
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- cpu_off : Function ID for CPU_OFF operation
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- cpu_on : Function ID for CPU_ON operation
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- migrate : Function ID for MIGRATE operation
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Example:
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0x95c10000>;
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cpu_off = <0x95c10001>;
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cpu_on = <0x95c10002>;
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migrate = <0x95c10003>;
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};
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@@ -293,7 +293,7 @@ kvm_run' (see below).
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4.11 KVM_GET_REGS
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Capability: basic
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Architectures: all
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Architectures: all except ARM
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Type: vcpu ioctl
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Parameters: struct kvm_regs (out)
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Returns: 0 on success, -1 on error
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@@ -314,7 +314,7 @@ struct kvm_regs {
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4.12 KVM_SET_REGS
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Capability: basic
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Architectures: all
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Architectures: all except ARM
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Type: vcpu ioctl
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Parameters: struct kvm_regs (in)
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Returns: 0 on success, -1 on error
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@@ -600,7 +600,7 @@ struct kvm_fpu {
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4.24 KVM_CREATE_IRQCHIP
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Capability: KVM_CAP_IRQCHIP
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Architectures: x86, ia64
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Architectures: x86, ia64, ARM
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Type: vm ioctl
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Parameters: none
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Returns: 0 on success, -1 on error
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@@ -608,21 +608,39 @@ Returns: 0 on success, -1 on error
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Creates an interrupt controller model in the kernel. On x86, creates a virtual
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ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a
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local APIC. IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23
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only go to the IOAPIC. On ia64, a IOSAPIC is created.
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only go to the IOAPIC. On ia64, a IOSAPIC is created. On ARM, a GIC is
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created.
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4.25 KVM_IRQ_LINE
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Capability: KVM_CAP_IRQCHIP
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Architectures: x86, ia64
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Architectures: x86, ia64, arm
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Type: vm ioctl
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Parameters: struct kvm_irq_level
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Returns: 0 on success, -1 on error
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Sets the level of a GSI input to the interrupt controller model in the kernel.
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Requires that an interrupt controller model has been previously created with
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KVM_CREATE_IRQCHIP. Note that edge-triggered interrupts require the level
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to be set to 1 and then back to 0.
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On some architectures it is required that an interrupt controller model has
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been previously created with KVM_CREATE_IRQCHIP. Note that edge-triggered
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interrupts require the level to be set to 1 and then back to 0.
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ARM can signal an interrupt either at the CPU level, or at the in-kernel irqchip
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(GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for
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specific cpus. The irq field is interpreted like this:
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bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 |
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field: | irq_type | vcpu_index | irq_id |
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The irq_type field has the following values:
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- irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ
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- irq_type[1]: in-kernel GIC: SPI, irq_id between 32 and 1019 (incl.)
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(the vcpu_index field is ignored)
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- irq_type[2]: in-kernel GIC: PPI, irq_id between 16 and 31 (incl.)
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(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)
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In both cases, level is used to raise/lower the line.
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struct kvm_irq_level {
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union {
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@@ -1775,6 +1793,27 @@ registers, find a list below:
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PPC | KVM_REG_PPC_VPA_DTL | 128
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PPC | KVM_REG_PPC_EPCR | 32
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ARM registers are mapped using the lower 32 bits. The upper 16 of that
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is the register group type, or coprocessor number:
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ARM core registers have the following id bit patterns:
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0x4002 0000 0010 <index into the kvm_regs struct:16>
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ARM 32-bit CP15 registers have the following id bit patterns:
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0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
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ARM 64-bit CP15 registers have the following id bit patterns:
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0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>
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ARM CCSIDR registers are demultiplexed by CSSELR value:
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0x4002 0000 0011 00 <csselr:8>
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ARM 32-bit VFP control registers have the following id bit patterns:
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0x4002 0000 0012 1 <regno:12>
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ARM 64-bit FP registers have the following id bit patterns:
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0x4002 0000 0012 0 <regno:12>
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4.69 KVM_GET_ONE_REG
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Capability: KVM_CAP_ONE_REG
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@@ -2127,6 +2166,50 @@ written, then `n_invalid' invalid entries, invalidating any previously
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valid entries found.
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4.77 KVM_ARM_VCPU_INIT
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Capability: basic
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Architectures: arm
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Type: vcpu ioctl
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Parameters: struct struct kvm_vcpu_init (in)
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Returns: 0 on success; -1 on error
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Errors:
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EINVAL: the target is unknown, or the combination of features is invalid.
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ENOENT: a features bit specified is unknown.
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This tells KVM what type of CPU to present to the guest, and what
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optional features it should have. This will cause a reset of the cpu
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registers to their initial values. If this is not called, KVM_RUN will
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return ENOEXEC for that vcpu.
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Note that because some registers reflect machine topology, all vcpus
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should be created before this ioctl is invoked.
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Possible features:
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- KVM_ARM_VCPU_POWER_OFF: Starts the CPU in a power-off state.
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Depends on KVM_CAP_ARM_PSCI.
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4.78 KVM_GET_REG_LIST
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Capability: basic
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Architectures: arm
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Type: vcpu ioctl
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Parameters: struct kvm_reg_list (in/out)
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Returns: 0 on success; -1 on error
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Errors:
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E2BIG: the reg index list is too big to fit in the array specified by
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the user (the number required will be written into n).
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struct kvm_reg_list {
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__u64 n; /* number of registers in reg[] */
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__u64 reg[0];
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};
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This ioctl returns the guest registers that are supported for the
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KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.
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5. The kvm_run structure
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------------------------
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