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[PATCH] ARM SMP: Add ARMv6 memory barriers

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Convert explicit gcc asm-based memory barriers into smp_mb() calls.
These change between barrier() and the ARMv6 data memory barrier
instruction depending on whether ARMv6 SMP is enabled.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2005-07-26 19:44:26 +01:00
committed by Russell King
parent 9560782f9a
commit 6d9b37a3a8
4 changed files with 67 additions and 27 deletions
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36
include/asm-arm/locks.h
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@@ -28,7 +28,8 @@
" blmi " #fail \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
})
#define __down_op_ret(ptr,fail) \
@@ -48,12 +49,14 @@
" mov %0, ip" \
: "=&r" (ret) \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
ret; \
})
#define __up_op(ptr,wake) \
({ \
smp_mb(); \
__asm__ __volatile__( \
"@ up_op\n" \
"1: ldrex lr, [%0]\n" \
@@ -66,7 +69,7 @@
" blle " #wake \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
})
/*
@@ -92,11 +95,13 @@
" blne " #fail \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
})
#define __up_op_write(ptr,wake) \
({ \
smp_mb(); \
__asm__ __volatile__( \
"@ up_op_read\n" \
"1: ldrex lr, [%0]\n" \
@@ -108,7 +113,7 @@
" blcs " #wake \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
})
#define __down_op_read(ptr,fail) \
@@ -116,6 +121,7 @@
#define __up_op_read(ptr,wake) \
({ \
smp_mb(); \
__asm__ __volatile__( \
"@ up_op_read\n" \
"1: ldrex lr, [%0]\n" \
@@ -128,7 +134,7 @@
" bleq " #wake \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
})
#else
@@ -148,7 +154,8 @@
" blmi " #fail \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
})
#define __down_op_ret(ptr,fail) \
@@ -169,12 +176,14 @@
" mov %0, ip" \
: "=&r" (ret) \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
ret; \
})
#define __up_op(ptr,wake) \
({ \
smp_mb(); \
__asm__ __volatile__( \
"@ up_op\n" \
" mrs ip, cpsr\n" \
@@ -188,7 +197,7 @@
" blle " #wake \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
})
/*
@@ -215,7 +224,8 @@
" blne " #fail \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
})
#define __up_op_write(ptr,wake) \
@@ -233,7 +243,8 @@
" blcs " #wake \
: \
: "r" (ptr), "I" (RW_LOCK_BIAS) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
smp_mb(); \
})
#define __down_op_read(ptr,fail) \
@@ -241,6 +252,7 @@
#define __up_op_read(ptr,wake) \
({ \
smp_mb(); \
__asm__ __volatile__( \
"@ up_op_read\n" \
" mrs ip, cpsr\n" \
@@ -254,7 +266,7 @@
" bleq " #wake \
: \
: "r" (ptr), "I" (1) \
: "ip", "lr", "cc", "memory"); \
: "ip", "lr", "cc"); \
})
#endif