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mfd: tps65217: Update register interrupt mask bits instead of writing operation

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TPS65217 interrupt register includes read/writeable mask bits with
read-only status bits. (bit 4, 5, 6 are R/W, bit 0, 1, 2 are RO)
And reserved bit is not required.

Register update operation is preferred for disabling all interrupts during
the device initialisation.

Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Milo Kim
2016-11-15 22:02:13 +09:00
committed by Lee Jones
parent f660206403
commit 6d2c2b9f80
2 changed files with 5 additions and 5 deletions
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3
include/linux/mfd/tps65217.h
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@@ -73,13 +73,14 @@
#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
#define TPS65217_INT_RESERVEDM BIT(7)
#define TPS65217_INT_PBM BIT(6)
#define TPS65217_INT_ACM BIT(5)
#define TPS65217_INT_USBM BIT(4)
#define TPS65217_INT_PBI BIT(2)
#define TPS65217_INT_ACI BIT(1)
#define TPS65217_INT_USBI BIT(0)
#define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \
TPS65217_INT_USBM)
#define TPS65217_CHGCONFIG0_TREG BIT(7)
#define TPS65217_CHGCONFIG0_DPPM BIT(6)