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clk: samsung: exynos7: add clocks for MMC block

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Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Naveen Krishna Ch
2014-10-21 11:13:52 +05:30
committed by Sylwester Nawrocki
parent 57a2b485fa
commit 6d0c8c723f
3 changed files with 265 additions and 0 deletions
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20
include/dt-bindings/clock/exynos7-clk.h
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@@ -27,6 +27,17 @@
#define CLK_SCLK_UART3 6
#define TOP0_NR_CLK 7
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
#define DOUT_ACLK_FSYS0_200 2
#define DOUT_SCLK_MMC2 3
#define DOUT_SCLK_MMC1 4
#define DOUT_SCLK_MMC0 5
#define CLK_SCLK_MMC2 6
#define CLK_SCLK_MMC1 7
#define CLK_SCLK_MMC0 8
#define TOP1_NR_CLK 9
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
@@ -58,4 +69,13 @@
#define SCLK_CHIPID 2
#define PERIS_NR_CLK 3
/* FSYS0 */
#define ACLK_MMC2 1
#define FSYS0_NR_CLK 2
/* FSYS1 */
#define ACLK_MMC1 1
#define ACLK_MMC0 2
#define FSYS1_NR_CLK 3
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */