Merge tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH:
"Here is the big char/misc driver pull request for 5.4-rc1.
As has been happening in previous releases, more and more individual
driver subsystem trees are ending up in here. Now if that is good or
bad I can't tell, but hopefully it makes your life easier as it's more
of an aggregation of trees together to one merge point for you.
Anyway, lots of stuff in here:
- habanalabs driver updates
- thunderbolt driver updates
- misc driver updates
- coresight and intel_th hwtracing driver updates
- fpga driver updates
- extcon driver updates
- some dma driver updates
- char driver updates
- android binder driver updates
- nvmem driver updates
- phy driver updates
- parport driver fixes
- pcmcia driver fix
- uio driver updates
- w1 driver updates
- configfs fixes
- other assorted driver updates
All of these have been in linux-next for a long time with no reported
issues"
* tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (200 commits)
misc: mic: Use PTR_ERR_OR_ZERO rather than its implementation
habanalabs: correctly cast variable to __le32
habanalabs: show correct id in error print
habanalabs: stop using the acronym KMD
habanalabs: display card name as sensors header
habanalabs: add uapi to retrieve aggregate H/W events
habanalabs: add uapi to retrieve device utilization
habanalabs: Make the Coresight timestamp perpetual
habanalabs: explicitly set the queue-id enumerated numbers
habanalabs: print to kernel log when reset is finished
habanalabs: replace __le32_to_cpu with le32_to_cpu
habanalabs: replace __cpu_to_le32/64 with cpu_to_le32/64
habanalabs: Handle HW_IP_INFO if device disabled or in reset
habanalabs: Expose devices after initialization is done
habanalabs: improve security in Debug IOCTL
habanalabs: use default structure for user input in Debug IOCTL
habanalabs: Add descriptive name to PSOC app status register
habanalabs: Add descriptive names to PSOC scratch-pad registers
habanalabs: create two char devices per ASIC
habanalabs: change device_setup_cdev() to be more generic
...
This commit is contained in:
Linus Torvalds
@@ -12,7 +12,8 @@ Description: (RW) Configure MSC operating mode:
|
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- "single", for contiguous buffer mode (high-order alloc);
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- "multi", for multiblock mode;
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- "ExI", for DCI handler mode;
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- "debug", for debug mode.
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- "debug", for debug mode;
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- any of the currently loaded buffer sinks.
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If operating mode changes, existing buffer is deallocated,
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provided there are no active users and tracing is not enabled,
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otherwise the write will fail.
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128
Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
Normal file
128
Documentation/ABI/testing/sysfs-devices-platform-stratix10-rsu
Normal file
@@ -0,0 +1,128 @@
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Intel Stratix10 Remote System Update (RSU) device attributes
|
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|
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What: /sys/devices/platform/stratix10-rsu.0/current_image
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Date: August 2019
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KernelVersion: 5.4
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) the address in flash of currently running image.
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|
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What: /sys/devices/platform/stratix10-rsu.0/fail_image
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Date: August 2019
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KernelVersion: 5.4
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) the address in flash of failed image.
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|
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What: /sys/devices/platform/stratix10-rsu.0/state
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Date: August 2019
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KernelVersion: 5.4
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) the state of RSU system.
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The state field has two parts: major error code in
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upper 16 bits and minor error code in lower 16 bits.
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b[15:0]
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Currently used only when major error is 0xF006
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(CPU watchdog timeout), in which case the minor
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error code is the value reported by CPU to
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firmware through the RSU notify command before
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the watchdog timeout occurs.
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b[31:16]
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0xF001 bitstream error
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0xF002 hardware access failure
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0xF003 bitstream corruption
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0xF004 internal error
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0xF005 device error
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0xF006 CPU watchdog timeout
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0xF007 internal unknown error
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|
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What: /sys/devices/platform/stratix10-rsu.0/version
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Date: August 2019
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KernelVersion: 5.4
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) the version number of RSU firmware. 19.3 or late
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version includes information about the firmware which
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reported the error.
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pre 19.3:
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b[31:0]
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0x0 version number
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19.3 or late:
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b[15:0]
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0x1 version number
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b[31:16]
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0x0 no error
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0x0DCF Decision CMF error
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0x0ACF Application CMF error
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What: /sys/devices/platform/stratix10-rsu.0/error_location
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Date: August 2019
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KernelVersion: 5.4
|
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) the error offset inside the image that failed.
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|
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What: /sys/devices/platform/stratix10-rsu.0/error_details
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Date: August 2019
|
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KernelVersion: 5.4
|
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
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(RO) error code.
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What: /sys/devices/platform/stratix10-rsu.0/retry_counter
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Date: August 2019
|
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KernelVersion: 5.4
|
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
|
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(RO) the current image's retry counter, which is used by
|
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user to know how many times the images is still allowed
|
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to reload itself before giving up and starting RSU
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fail-over flow.
|
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|
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What: /sys/devices/platform/stratix10-rsu.0/reboot_image
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Date: August 2019
|
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KernelVersion: 5.4
|
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
||||
Description:
|
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(WO) the address in flash of image to be loaded on next
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reboot command.
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What: /sys/devices/platform/stratix10-rsu.0/notify
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Date: August 2019
|
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KernelVersion: 5.4
|
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Contact: Richard Gong <richard.gong@linux.intel.com>
|
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Description:
|
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(WO) client to notify firmware with different actions.
|
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|
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b[15:0]
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inform firmware the current software execution
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stage.
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0 the first stage bootloader didn't run or
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didn't reach the point of launching second
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||||
stage bootloader.
|
||||
1 failed in second bootloader or didn't get
|
||||
to the point of launching the operating
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||||
system.
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2 both first and second stage bootloader ran
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and the operating system launch was
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attempted.
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||||
|
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b[16]
|
||||
1 firmware to reset current image retry
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||||
counter.
|
||||
0 no action.
|
||||
|
||||
b[17]
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||||
1 firmware to clear RSU log
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0 no action.
|
||||
|
||||
b[18]
|
||||
this is negative logic
|
||||
1 no action
|
||||
0 firmware record the notify code defined
|
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in b[15:0].
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@@ -57,6 +57,7 @@ KernelVersion: 5.1
|
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Contact: oded.gabbay@gmail.com
|
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Description: Allows the user to set the maximum clock frequency for MME, TPC
|
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and IC when the power management profile is set to "automatic".
|
||||
This property is valid only for the Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/ic_clk
|
||||
Date: Jan 2019
|
||||
@@ -127,8 +128,8 @@ Description: Power management profile. Values are "auto", "manual". In "auto"
|
||||
the max clock frequency to a low value when there are no user
|
||||
processes that are opened on the device's file. In "manual"
|
||||
mode, the user sets the maximum clock frequency by writing to
|
||||
ic_clk, mme_clk and tpc_clk
|
||||
|
||||
ic_clk, mme_clk and tpc_clk. This property is valid only for
|
||||
the Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/preboot_btl_ver
|
||||
Date: Jan 2019
|
||||
@@ -186,11 +187,4 @@ What: /sys/class/habanalabs/hl<n>/uboot_ver
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Version of the u-boot running on the device's CPU
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/write_open_cnt
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Displays the total number of user processes that are currently
|
||||
opened on the device's file
|
||||
Description: Version of the u-boot running on the device's CPU
|
||||
@@ -21,3 +21,88 @@ Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns Bitstream (static FPGA region) meta
|
||||
data, which includes the synthesis date, seed and other
|
||||
information of this static FPGA region.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/cache_size
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns cache size of this FPGA device.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/fabric_version
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns fabric version of this FPGA device.
|
||||
Userspace applications need this information to select
|
||||
best data channels per different fabric design.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/socket_id
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns socket_id to indicate which socket
|
||||
this FPGA belongs to, only valid for integrated solution.
|
||||
User only needs this information, in case standard numa node
|
||||
can't provide correct information.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie0_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-Write. Read this file for errors detected on pcie0 link.
|
||||
Write this file to clear errors logged in pcie0_errors. Write
|
||||
fails with -EINVAL if input parsing fails or input error code
|
||||
doesn't match.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie1_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-Write. Read this file for errors detected on pcie1 link.
|
||||
Write this file to clear errors logged in pcie1_errors. Write
|
||||
fails with -EINVAL if input parsing fails or input error code
|
||||
doesn't match.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/nonfatal_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns non-fatal errors detected.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/catfatal_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It returns catastrophic and fatal errors detected.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/inject_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-Write. Read this file to check errors injected. Write this
|
||||
file to inject errors for testing purpose. Write fails with
|
||||
-EINVAL if input parsing fails or input inject error code isn't
|
||||
supported.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/fme_errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-Write. Read this file to get errors detected on FME.
|
||||
Write this file to clear errors logged in fme_errors. Write
|
||||
fials with -EINVAL if input parsing fails or input error code
|
||||
doesn't match.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/first_error
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the first error detected by
|
||||
hardware.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-fme.0/errors/next_error
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the second error detected by
|
||||
hardware.
|
||||
|
||||
@@ -14,3 +14,88 @@ Description: Read-only. User can program different PR bitstreams to FPGA
|
||||
Accelerator Function Unit (AFU) for different functions. It
|
||||
returns uuid which could be used to identify which PR bitstream
|
||||
is programmed in this AFU.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/power_state
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. It reports the APx (AFU Power) state, different APx
|
||||
means different throttling level. When reading this file, it
|
||||
returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/ap1_event
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
|
||||
It's used to indicate transient AP1 state. Write 1 to this
|
||||
file to clear AP1 event.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/ap2_event
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-write. Read this file for AP2 (AFU Power State 2) event.
|
||||
It's used to indicate transient AP2 state. Write 1 to this
|
||||
file to clear AP2 event.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/ltr
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-write. Read or set AFU latency tolerance reporting value.
|
||||
Set ltr to 1 if the AFU can tolerate latency >= 40us or set it
|
||||
to 0 if it is latency sensitive.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcmd
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Write-only. User writes command to this interface to set
|
||||
userclock to AFU.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/userclk_freqsts
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the status of issued command
|
||||
to userclck_freqcmd.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcntrcmd
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Write-only. User writes command to this interface to set
|
||||
userclock counter.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/userclk_freqcntrsts
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the status of issued command
|
||||
to userclck_freqcntrcmd.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/errors/errors
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-Write. Read this file to get errors detected on port and
|
||||
Accelerated Function Unit (AFU). Write error code to this file
|
||||
to clear errors. Write fails with -EINVAL if input parsing
|
||||
fails or input error code doesn't match. Write fails with
|
||||
-EBUSY or -ETIMEDOUT if error can't be cleared as hardware
|
||||
in low power state (-EBUSY) or not respoding (-ETIMEDOUT).
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/errors/first_error
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the first error detected by
|
||||
hardware.
|
||||
|
||||
What: /sys/bus/platform/devices/dfl-port.0/errors/first_malformed_req
|
||||
Date: August 2019
|
||||
KernelVersion: 5.4
|
||||
Contact: Wu Hao <hao.wu@intel.com>
|
||||
Description: Read-only. Read this file to get the first malformed request
|
||||
captured by hardware.
|
||||
|
||||
@@ -136,7 +136,9 @@ Required properties:
|
||||
OCOTP bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8qxp-scu-ocotp"
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-scu-ocotp",
|
||||
"fsl,imx8qxp-scu-ocotp".
|
||||
- #address-cells: Must be 1. Contains byte index
|
||||
- #size-cells: Must be 1. Contains byte length
|
||||
|
||||
|
||||
@@ -72,5 +72,5 @@ codec: wm8280@0 {
|
||||
1 2 1 /* MICDET2 MICBIAS2 GPIO=high */
|
||||
>;
|
||||
|
||||
wlf,gpsw = <0>;
|
||||
wlf,gpsw = <ARIZONA_GPSW_OPEN>;
|
||||
};
|
||||
|
||||
@@ -5,7 +5,9 @@ controlled using I2C and enables USB data, stereo and mono audio, video,
|
||||
microphone, and UART data to use a common connector port.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "fcs,fsa9480"
|
||||
- compatible : Must be one of
|
||||
"fcs,fsa9480"
|
||||
"fcs,fsa880"
|
||||
- reg : Specifies i2c slave address. Must be 0x25.
|
||||
- interrupts : Should contain one entry specifying interrupt signal of
|
||||
interrupt parent to which interrupt pin of the chip is connected.
|
||||
|
||||
@@ -3,10 +3,7 @@ Altera FPGA To SDRAM Bridge Driver
|
||||
Required properties:
|
||||
- compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
|
||||
|
||||
Optional properties:
|
||||
- bridge-enable : 0 if driver should disable bridge at startup
|
||||
1 if driver should enable bridge at startup
|
||||
Default is to leave bridge in current state.
|
||||
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
|
||||
|
||||
Example:
|
||||
fpga_bridge3: fpga-bridge@ffc25080 {
|
||||
|
||||
@@ -10,10 +10,7 @@ Required properties:
|
||||
- compatible : Should contain "altr,freeze-bridge-controller"
|
||||
- regs : base address and size for freeze bridge module
|
||||
|
||||
Optional properties:
|
||||
- bridge-enable : 0 if driver should disable bridge at startup
|
||||
1 if driver should enable bridge at startup
|
||||
Default is to leave bridge in current state.
|
||||
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
|
||||
|
||||
Example:
|
||||
freeze-controller@100000450 {
|
||||
|
||||
@@ -9,10 +9,7 @@ Required properties:
|
||||
- resets : Phandle and reset specifier for this bridge's reset
|
||||
- clocks : Clocks used by this module.
|
||||
|
||||
Optional properties:
|
||||
- bridge-enable : 0 if driver should disable bridge at startup.
|
||||
1 if driver should enable bridge at startup.
|
||||
Default is to leave bridge in its current state.
|
||||
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
|
||||
|
||||
Example:
|
||||
fpga_bridge0: fpga-bridge@ff400000 {
|
||||
|
||||
13
Documentation/devicetree/bindings/fpga/fpga-bridge.txt
Normal file
13
Documentation/devicetree/bindings/fpga/fpga-bridge.txt
Normal file
@@ -0,0 +1,13 @@
|
||||
FPGA Bridge Device Tree Binding
|
||||
|
||||
Optional properties:
|
||||
- bridge-enable : 0 if driver should disable bridge at startup
|
||||
1 if driver should enable bridge at startup
|
||||
Default is to leave bridge in current state.
|
||||
|
||||
Example:
|
||||
fpga_bridge3: fpga-bridge@ffc25080 {
|
||||
compatible = "altr,socfpga-fpga2sdram-bridge";
|
||||
reg = <0xffc25080 0x4>;
|
||||
bridge-enable = <0>;
|
||||
};
|
||||
@@ -18,12 +18,8 @@ Required properties:
|
||||
- clocks : input clock to IP
|
||||
- clock-names : should contain "aclk"
|
||||
|
||||
Optional properties:
|
||||
- bridge-enable : 0 if driver should disable bridge at startup
|
||||
1 if driver should enable bridge at startup
|
||||
Default is to leave bridge in current state.
|
||||
|
||||
See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
|
||||
See Documentation/devicetree/bindings/fpga/fpga-region.txt and
|
||||
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
|
||||
|
||||
Example:
|
||||
fpga-bridge@100000450 {
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
Qualcomm QCS404 Network-On-Chip interconnect driver binding
|
||||
-----------------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
"qcom,qcs404-bimc"
|
||||
"qcom,qcs404-pcnoc"
|
||||
"qcom,qcs404-snoc"
|
||||
- #interconnect-cells : should contain 1
|
||||
|
||||
reg : specifies the physical base address and size of registers
|
||||
clocks : list of phandles and specifiers to all interconnect bus clocks
|
||||
clock-names : clock names should include both "bus" and "bus_a"
|
||||
|
||||
Example:
|
||||
|
||||
soc {
|
||||
...
|
||||
bimc: interconnect@400000 {
|
||||
reg = <0x00400000 0x80000>;
|
||||
compatible = "qcom,qcs404-bimc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
|
||||
<&rpmcc RPM_SMD_BIMC_A_CLK>;
|
||||
};
|
||||
|
||||
pnoc: interconnect@500000 {
|
||||
reg = <0x00500000 0x15080>;
|
||||
compatible = "qcom,qcs404-pcnoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_PNOC_A_CLK>;
|
||||
};
|
||||
|
||||
snoc: interconnect@580000 {
|
||||
reg = <0x00580000 0x23080>;
|
||||
compatible = "qcom,qcs404-snoc";
|
||||
#interconnect-cells = <1>;
|
||||
clock-names = "bus", "bus_a";
|
||||
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
|
||||
<&rpmcc RPM_SMD_SNOC_A_CLK>;
|
||||
};
|
||||
};
|
||||
@@ -2,7 +2,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
|
||||
|
||||
This binding represents the on-chip eFuse OTP controller found on
|
||||
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
|
||||
i.MX7D/S, i.MX7ULP and i.MX8MQ SoCs.
|
||||
i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM and i.MX8MN SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
@@ -16,6 +16,7 @@ Required properties:
|
||||
"fsl,imx7ulp-ocotp" (i.MX7ULP),
|
||||
"fsl,imx8mq-ocotp" (i.MX8MQ),
|
||||
"fsl,imx8mm-ocotp" (i.MX8MM),
|
||||
"fsl,imx8mn-ocotp" (i.MX8MN),
|
||||
followed by "syscon".
|
||||
- #address-cells : Should be 1
|
||||
- #size-cells : Should be 1
|
||||
|
||||
@@ -17,6 +17,14 @@ Required properties:
|
||||
name must be "core" for the first clock and "reg" for the second
|
||||
one
|
||||
|
||||
Optional properties:
|
||||
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
|
||||
Either 1, 2 or 4 PHYs might be needed depending on the number of
|
||||
PCIe lanes.
|
||||
- phy-names: names of the PHYs corresponding to the number of lanes.
|
||||
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
||||
2 PHYs.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f2600000 {
|
||||
|
||||
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
||||
properties:
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- lantiq,vrx200-pcie-phy
|
||||
- lantiq,arx300-pcie-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PHY module clock
|
||||
- description: PDI register clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: pdi
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: exclusive PHY reset line
|
||||
- description: shared reset line between the PCIe PHY and PCIe controller
|
||||
|
||||
resets-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: pcie
|
||||
|
||||
lantiq,rcu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the RCU syscon
|
||||
|
||||
lantiq,rcu-endian-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: the offset of the endian registers for this PHY instance in the RCU syscon
|
||||
|
||||
lantiq,rcu-big-endian-mask:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
|
||||
|
||||
big-endian:
|
||||
description: Configures the PDI (PHY) registers in big-endian mode
|
||||
type: boolean
|
||||
|
||||
little-endian:
|
||||
description: Configures the PDI (PHY) registers in big-endian mode
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- "#phy-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- lantiq,rcu
|
||||
- lantiq,rcu-endian-offset
|
||||
- lantiq,rcu-big-endian-mask
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pcie0_phy: phy@106800 {
|
||||
compatible = "lantiq,vrx200-pcie-phy";
|
||||
reg = <0x106800 0x100>;
|
||||
lantiq,rcu = <&rcu0>;
|
||||
lantiq,rcu-endian-offset = <0x4c>;
|
||||
lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
|
||||
big-endian;
|
||||
clocks = <&pmu 32>, <&pmu 36>;
|
||||
clock-names = "phy", "pdi";
|
||||
resets = <&reset0 12 24>, <&reset0 22 22>;
|
||||
reset-names = "phy", "pcie";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -25,6 +25,13 @@ Required properties:
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 0.
|
||||
|
||||
Optional properlties:
|
||||
|
||||
- clocks: pointers to the reference clocks for this device (CP110 only),
|
||||
consequently: MG clock, MG Core clock, AXI clock.
|
||||
- clock-names: names of used clocks for CP110 only, must be :
|
||||
"mg_clk", "mg_core_clk" and "axi_clk".
|
||||
|
||||
A sub-node is required for each comphy lane provided by the comphy.
|
||||
|
||||
Required properties (child nodes):
|
||||
@@ -39,6 +46,9 @@ Examples:
|
||||
compatible = "marvell,comphy-cp110";
|
||||
reg = <0x120000 0x6000>;
|
||||
marvell,system-controller = <&cpm_syscon0>;
|
||||
clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
|
||||
<&CP110_LABEL(clk) 1 18>;
|
||||
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@@ -408,6 +408,13 @@ handler code. You also do not need to know anything about the chip's
|
||||
internal registers to create the kernel part of the driver. All you need
|
||||
to know is the irq number of the pin the chip is connected to.
|
||||
|
||||
When used in a device-tree enabled system, the driver needs to be
|
||||
probed with the ``"of_id"`` module parameter set to the ``"compatible"``
|
||||
string of the node the driver is supposed to handle. By default, the
|
||||
node's name (without the unit address) is exposed as name for the
|
||||
UIO device in userspace. To set a custom name, a property named
|
||||
``"linux,uio-name"`` may be specified in the DT node.
|
||||
|
||||
Using uio_dmem_genirq for platform devices
|
||||
------------------------------------------
|
||||
|
||||
|
||||
@@ -87,6 +87,8 @@ The following functions are exposed through ioctls:
|
||||
- Get driver API version (DFL_FPGA_GET_API_VERSION)
|
||||
- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
|
||||
- Program bitstream (DFL_FPGA_FME_PORT_PR)
|
||||
- Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
|
||||
- Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
|
||||
|
||||
More functions are exposed through sysfs
|
||||
(/sys/class/fpga_region/regionX/dfl-fme.n/):
|
||||
@@ -102,6 +104,10 @@ More functions are exposed through sysfs
|
||||
one FPGA device may have more than one port, this sysfs interface indicates
|
||||
how many ports the FPGA device has.
|
||||
|
||||
Global error reporting management (errors/)
|
||||
error reporting sysfs interfaces allow user to read errors detected by the
|
||||
hardware, and clear the logged errors.
|
||||
|
||||
|
||||
FIU - PORT
|
||||
==========
|
||||
@@ -143,6 +149,10 @@ More functions are exposed through sysfs:
|
||||
Read Accelerator GUID (afu_id)
|
||||
afu_id indicates which PR bitstream is programmed to this AFU.
|
||||
|
||||
Error reporting (errors/)
|
||||
error reporting sysfs interfaces allow user to read port/afu errors
|
||||
detected by the hardware, and clear the logged errors.
|
||||
|
||||
|
||||
DFL Framework Overview
|
||||
======================
|
||||
@@ -218,6 +228,101 @@ the compat_id exposed by the target FPGA region. This check is usually done by
|
||||
userspace before calling the reconfiguration IOCTL.
|
||||
|
||||
|
||||
FPGA virtualization - PCIe SRIOV
|
||||
================================
|
||||
This section describes the virtualization support on DFL based FPGA device to
|
||||
enable accessing an accelerator from applications running in a virtual machine
|
||||
(VM). This section only describes the PCIe based FPGA device with SRIOV support.
|
||||
|
||||
Features supported by the particular FPGA device are exposed through Device
|
||||
Feature Lists, as illustrated below:
|
||||
|
||||
::
|
||||
|
||||
+-------------------------------+ +-------------+
|
||||
| PF | | VF |
|
||||
+-------------------------------+ +-------------+
|
||||
^ ^ ^ ^
|
||||
| | | |
|
||||
+-----|------------|---------|--------------|-------+
|
||||
| | | | | |
|
||||
| +-----+ +-------+ +-------+ +-------+ |
|
||||
| | FME | | Port0 | | Port1 | | Port2 | |
|
||||
| +-----+ +-------+ +-------+ +-------+ |
|
||||
| ^ ^ ^ |
|
||||
| | | | |
|
||||
| +-------+ +------+ +-------+ |
|
||||
| | AFU | | AFU | | AFU | |
|
||||
| +-------+ +------+ +-------+ |
|
||||
| |
|
||||
| DFL based FPGA PCIe Device |
|
||||
+---------------------------------------------------+
|
||||
|
||||
FME is always accessed through the physical function (PF).
|
||||
|
||||
Ports (and related AFUs) are accessed via PF by default, but could be exposed
|
||||
through virtual function (VF) devices via PCIe SRIOV. Each VF only contains
|
||||
1 Port and 1 AFU for isolation. Users could assign individual VFs (accelerators)
|
||||
created via PCIe SRIOV interface, to virtual machines.
|
||||
|
||||
The driver organization in virtualization case is illustrated below:
|
||||
::
|
||||
|
||||
+-------++------++------+ |
|
||||
| FME || FME || FME | |
|
||||
| FPGA || FPGA || FPGA | |
|
||||
|Manager||Bridge||Region| |
|
||||
+-------++------++------+ |
|
||||
+-----------------------+ +--------+ | +--------+
|
||||
| FME | | AFU | | | AFU |
|
||||
| Module | | Module | | | Module |
|
||||
+-----------------------+ +--------+ | +--------+
|
||||
+-----------------------+ | +-----------------------+
|
||||
| FPGA Container Device | | | FPGA Container Device |
|
||||
| (FPGA Base Region) | | | (FPGA Base Region) |
|
||||
+-----------------------+ | +-----------------------+
|
||||
+------------------+ | +------------------+
|
||||
| FPGA PCIE Module | | Virtual | FPGA PCIE Module |
|
||||
+------------------+ Host | Machine +------------------+
|
||||
-------------------------------------- | ------------------------------
|
||||
+---------------+ | +---------------+
|
||||
| PCI PF Device | | | PCI VF Device |
|
||||
+---------------+ | +---------------+
|
||||
|
||||
FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
|
||||
is detected. It:
|
||||
|
||||
* Finishes enumeration on both FPGA PCIe PF and VF device using common
|
||||
interfaces from DFL framework.
|
||||
* Supports SRIOV.
|
||||
|
||||
The FME device driver plays a management role in this driver architecture, it
|
||||
provides ioctls to release Port from PF and assign Port to PF. After release
|
||||
a port from PF, then it's safe to expose this port through a VF via PCIe SRIOV
|
||||
sysfs interface.
|
||||
|
||||
To enable accessing an accelerator from applications running in a VM, the
|
||||
respective AFU's port needs to be assigned to a VF using the following steps:
|
||||
|
||||
#. The PF owns all AFU ports by default. Any port that needs to be
|
||||
reassigned to a VF must first be released through the
|
||||
DFL_FPGA_FME_PORT_RELEASE ioctl on the FME device.
|
||||
|
||||
#. Once N ports are released from PF, then user can use command below
|
||||
to enable SRIOV and VFs. Each VF owns only one Port with AFU.
|
||||
|
||||
::
|
||||
|
||||
echo N > $PCI_DEVICE_PATH/sriov_numvfs
|
||||
|
||||
#. Pass through the VFs to VMs
|
||||
|
||||
#. The AFU under VF is accessible from applications in VM (using the
|
||||
same driver inside the VF).
|
||||
|
||||
Note that an FME can't be assigned to a VF, thus PR and other management
|
||||
functions are only available via the PF.
|
||||
|
||||
Device enumeration
|
||||
==================
|
||||
This section introduces how applications enumerate the fpga device from
|
||||
|
||||
@@ -20,3 +20,4 @@ fit into other categories.
|
||||
isl29003
|
||||
lis3lv02d
|
||||
max6875
|
||||
xilinx_sdfec
|
||||
|
||||
Reference in New Issue
Block a user