Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
This commit is contained in:
Linus Torvalds
@@ -32,6 +32,7 @@ config ARMADA_370_XP_TIMER
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config MESON6_TIMER
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bool
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select CLKSRC_MMIO
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config ORION_TIMER
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select CLKSRC_OF
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@@ -45,4 +45,5 @@ obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
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obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
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obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o
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obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
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@@ -43,6 +43,7 @@
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#include <linux/module.h>
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#include <linux/sched_clock.h>
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#include <linux/percpu.h>
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#include <linux/syscore_ops.h>
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/*
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* Timer block registers.
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@@ -223,6 +224,28 @@ static struct notifier_block armada_370_xp_timer_cpu_nb = {
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.notifier_call = armada_370_xp_timer_cpu_notify,
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};
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static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
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static int armada_370_xp_timer_suspend(void)
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{
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timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
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timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
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return 0;
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}
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static void armada_370_xp_timer_resume(void)
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{
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
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writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
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}
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struct syscore_ops armada_370_xp_timer_syscore_ops = {
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.suspend = armada_370_xp_timer_suspend,
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.resume = armada_370_xp_timer_resume,
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};
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static void __init armada_370_xp_timer_common_init(struct device_node *np)
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{
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u32 clr = 0, set = 0;
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@@ -285,6 +308,8 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
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/* Immediately configure the timer on the boot CPU */
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if (!res)
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armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
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register_syscore_ops(&armada_370_xp_timer_syscore_ops);
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}
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static void __init armada_xp_timer_init(struct device_node *np)
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210
drivers/clocksource/timer-integrator-ap.c
Normal file
210
drivers/clocksource/timer-integrator-ap.c
Normal file
@@ -0,0 +1,210 @@
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/*
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* Integrator/AP timer driver
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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* Copyright (c) 2014, Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <asm/hardware/arm_timer.h>
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static void __iomem * sched_clk_base;
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static u64 notrace integrator_read_sched_clock(void)
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{
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return -readl(sched_clk_base + TIMER_VALUE);
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}
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static void integrator_clocksource_init(unsigned long inrate,
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void __iomem *base)
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{
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u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
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unsigned long rate = inrate;
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if (rate >= 1500000) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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writel(0xffff, base + TIMER_LOAD);
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writel(ctrl, base + TIMER_CTRL);
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clocksource_mmio_init(base + TIMER_VALUE, "timer2",
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rate, 200, 16, clocksource_mmio_readl_down);
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sched_clk_base = base;
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sched_clock_register(integrator_read_sched_clock, 16, rate);
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}
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static unsigned long timer_reload;
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static void __iomem * clkevt_base;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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/* Disable timer */
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writel(ctrl, clkevt_base + TIMER_CTRL);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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/* Enable the timer and start the periodic tick */
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Leave the timer disabled, .set_next_event will enable it */
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ctrl &= ~TIMER_CTRL_PERIODIC;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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default:
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/* Just leave in disabled state */
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break;
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}
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(unsigned long inrate,
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void __iomem *base, int irq)
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{
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unsigned long rate = inrate;
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unsigned int ctrl = 0;
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clkevt_base = base;
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/* Calculate and program a divisor */
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if (rate > 0x100000 * HZ) {
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rate /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (rate > 0x10000 * HZ) {
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rate /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = rate / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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setup_irq(irq, &integrator_timer_irq);
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clockevents_config_and_register(&integrator_clockevent,
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rate,
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1,
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0xffffU);
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}
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static void __init integrator_ap_timer_init_of(struct device_node *node)
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{
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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struct clk *clk;
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unsigned long rate;
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struct device_node *pri_node;
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struct device_node *sec_node;
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base = of_io_request_and_map(node, 0, "integrator-timer");
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if (!base)
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return;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("No clock for %s\n", node->name);
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return;
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}
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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writel(0, base + TIMER_CTRL);
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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pri_node = of_find_node_by_path(path);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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sec_node = of_find_node_by_path(path);
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if (node == pri_node) {
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/* The primary timer lacks IRQ, use as clocksource */
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integrator_clocksource_init(rate, base);
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return;
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}
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if (node == sec_node) {
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/* The secondary timer will drive the clock event */
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irq = irq_of_parse_and_map(node, 0);
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integrator_clockevent_init(rate, base, irq);
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return;
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}
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pr_info("Timer @%p unused\n", base);
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clk_disable_unprepare(clk);
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}
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CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
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integrator_ap_timer_init_of);
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