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drm/amdgpu/display: Fix Pollock Variant Detection

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Problem Description:
Currently we are checking internal fused rev id with pci rev id. However, fused
internal rev id is the same on all raven2 parts (in which Dali and Pollock were
based on too), thus Pollock detection fails

Fix:
use the pci rev to preform the detection for bandwidth calculations.

Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Aly-Tawfik <altawfik@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aly-Tawfik
2020-02-25 15:01:28 -05:00
committed by Alex Deucher
parent 2dc31ca189
commit 6cc47f3f96
2 changed files with 11 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/amd/display/include/dal_asic_id.h
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@@ -134,11 +134,6 @@
#define PICASSO_A0 0x41
/* DCN1_01 */
#define RAVEN2_A0 0x81
#define RAVEN2_15D8_REV_94 0x94
#define RAVEN2_15D8_REV_95 0x95
#define RAVEN2_15D8_REV_E9 0xE9
#define RAVEN2_15D8_REV_EA 0xEA
#define RAVEN2_15D8_REV_EB 0xEB
#define RAVEN1_F0 0xF0
#define RAVEN_UNKNOWN 0xFF
#ifndef ASICREV_IS_RAVEN
@@ -149,16 +144,17 @@
#define PRID_DALI_E3 0xE3
#define PRID_DALI_E4 0xE4
#define PRID_POLLOCK_94 0x94
#define PRID_POLLOCK_95 0x95
#define PRID_POLLOCK_E9 0xE9
#define PRID_POLLOCK_EA 0xEA
#define PRID_POLLOCK_EB 0xEB
#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
#ifndef ASICREV_IS_RAVEN2
#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
#endif
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
#define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \
|| eChipRev == RAVEN2_15D8_REV_95 \
|| eChipRev == RAVEN2_15D8_REV_E9 \
|| eChipRev == RAVEN2_15D8_REV_EA \
|| eChipRev == RAVEN2_15D8_REV_EB)
#define FAMILY_RV 142 /* DCN 1*/