ARM: owl: smp: Drop owl_secondary_boot()
Commit18cfd9429d
simplified the S500 SMP code by removing a loop for pen_release in owl_secondary_boot(). Since then it is only calling owl_v7_invalidate_l1() before branching to secondary_startup(). The owl_v7_invalidate_l1() assembler function is superfluous, too. Therefore drop owl_secondary_boot() and use secondary_boot() directly. Fixes:18cfd9429d
("ARM: owl: smp: Drop bogus holding pen") Cc: David Liu <liuwei@actions-semi.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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@@ -1,3 +1 @@
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obj-${CONFIG_SMP} += platsmp.o headsmp.o
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obj-${CONFIG_SMP} += platsmp.o
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AFLAGS_headsmp.o := -Wa,-march=armv7-a
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@@ -1,52 +0,0 @@
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/*
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* Copyright 2012 Actions Semi Inc.
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* Author: Actions Semi, Inc.
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*
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* Copyright (c) 2017 Andreas Färber
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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ENTRY(owl_v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(owl_v7_invalidate_l1)
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ENTRY(owl_secondary_startup)
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bl owl_v7_invalidate_l1
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b secondary_startup
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@@ -71,7 +71,7 @@ static int s500_wakeup_secondary(unsigned int cpu)
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/* wait for CPUx to run to WFE instruction */
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/* wait for CPUx to run to WFE instruction */
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udelay(200);
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udelay(200);
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writel(__pa_symbol(owl_secondary_startup),
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writel(__pa_symbol(secondary_startup),
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timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
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timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
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writel(OWL_CPUx_FLAG_BOOT,
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writel(OWL_CPUx_FLAG_BOOT,
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timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
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timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
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