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memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling

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In certain situations, such as when returning from low power modes, the
EMIF must re-run hardware leveling to properly restore DDR3 access.

This is accomplished by introducing a new ti-emif-sram-pm call,
ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
the full write and read leveling processes.

Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Dave Gerlach
2019-04-02 11:57:42 -05:00
committed by Tony Lindgren
parent 9e98c678c2
commit 6c110561eb
4 changed files with 51 additions and 0 deletions
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3
include/linux/ti-emif-sram.h
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@@ -55,6 +55,7 @@ struct ti_emif_pm_data {
struct ti_emif_pm_functions {
u32 save_context;
u32 restore_context;
u32 run_hw_leveling;
u32 enter_sr;
u32 exit_sr;
u32 abort_sr;
@@ -126,6 +127,8 @@ static inline void ti_emif_asm_offsets(void)
offsetof(struct ti_emif_pm_functions, save_context));
DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
offsetof(struct ti_emif_pm_functions, restore_context));
DEFINE(EMIF_PM_RUN_HW_LEVELING,
offsetof(struct ti_emif_pm_functions, run_hw_leveling));
DEFINE(EMIF_PM_ENTER_SR_OFFSET,
offsetof(struct ti_emif_pm_functions, enter_sr));
DEFINE(EMIF_PM_EXIT_SR_OFFSET,