mtd: generic FSMC NAND MTD driver
This is the same driver submitted by ST Micros SPEAr team but generalized and tested on the ST-Ericsson U300. It probably easily works on the NHK8815 too. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Linus Walleij
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David Woodhouse
David Woodhouse
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include/linux/mtd/fsmc.h
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include/linux/mtd/fsmc.h
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/*
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* incude/mtd/fsmc.h
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*
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* ST Microelectronics
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* Flexible Static Memory Controller (FSMC)
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* platform data interface and header file
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*
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* Copyright © 2010 ST Microelectronics
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* Vipin Kumar <vipin.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MTD_FSMC_H
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#define __MTD_FSMC_H
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/types.h>
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#include <linux/mtd/partitions.h>
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#include <asm/param.h>
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#define FSMC_NAND_BW8 1
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#define FSMC_NAND_BW16 2
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/*
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* The placement of the Command Latch Enable (CLE) and
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* Address Latch Enable (ALE) is twised around in the
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* SPEAR310 implementation.
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*/
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#if defined(CONFIG_MACH_SPEAR310)
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#define PLAT_NAND_CLE (1 << 17)
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#define PLAT_NAND_ALE (1 << 16)
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#else
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#define PLAT_NAND_CLE (1 << 16)
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#define PLAT_NAND_ALE (1 << 17)
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#endif
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#define FSMC_MAX_NOR_BANKS 4
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#define FSMC_MAX_NAND_BANKS 4
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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struct fsmc_nor_bank_regs {
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uint32_t ctrl;
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uint32_t ctrl_tim;
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};
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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/* ctrl_tim register definitions */
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struct fsms_nand_bank_regs {
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uint32_t pc;
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uint32_t sts;
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uint32_t comm;
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uint32_t attrib;
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uint32_t ioata;
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uint32_t ecc1;
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uint32_t ecc2;
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uint32_t ecc3;
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};
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#define FSMC_NOR_REG_SIZE 0x40
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struct fsmc_regs {
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struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
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uint8_t reserved_1[0x40 - 0x20];
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struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
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uint8_t reserved_2[0xfe0 - 0xc0];
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uint32_t peripid0; /* 0xfe0 */
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uint32_t peripid1; /* 0xfe4 */
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uint32_t peripid2; /* 0xfe8 */
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uint32_t peripid3; /* 0xfec */
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uint32_t pcellid0; /* 0xff0 */
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uint32_t pcellid1; /* 0xff4 */
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uint32_t pcellid2; /* 0xff8 */
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uint32_t pcellid3; /* 0xffc */
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};
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1 << 9)
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#define FSMC_TAR_1 (1 << 13)
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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/* comm register definitions */
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#define FSMC_TSET_0 (0 << 0)
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#define FSMC_TWAIT_6 (6 << 8)
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#define FSMC_THOLD_4 (4 << 16)
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#define FSMC_THIZ_1 (1 << 24)
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/* peripid2 register definitions */
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#define FSMC_REVISION_MSK (0xf)
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#define FSMC_REVISION_SHFT (0x4)
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#define FSMC_VER1 1
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#define FSMC_VER2 2
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#define FSMC_VER3 3
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#define FSMC_VER4 4
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#define FSMC_VER5 5
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#define FSMC_VER6 6
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#define FSMC_VER7 7
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#define FSMC_VER8 8
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static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
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{
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return (readl(®s->peripid2) >> FSMC_REVISION_SHFT) &
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FSMC_REVISION_MSK;
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}
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/*
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* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
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* and it has to be read consecutively and immediately after the 512
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* byte data block for hardware to generate the error bit offsets
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* Managing the ecc bytes in the following way is easier. This way is
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* similar to oobfree structure maintained already in u-boot nand driver
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*/
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#define MAX_ECCPLACE_ENTRIES 32
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struct fsmc_nand_eccplace {
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uint8_t offset;
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uint8_t length;
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};
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struct fsmc_eccplace {
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struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
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};
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/**
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* fsmc_nand_platform_data - platform specific NAND controller config
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* @partitions: partition table for the platform, use a default fallback
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* if this is NULL
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* @nr_partitions: the number of partitions in the previous entry
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* @options: different options for the driver
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* @width: bus width
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* @bank: default bank
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* @select_bank: callback to select a certain bank, this is
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* platform-specific. If the controller only supports one bank
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* this may be set to NULL
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*/
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struct fsmc_nand_platform_data {
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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unsigned int options;
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unsigned int width;
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unsigned int bank;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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};
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extern int __init fsmc_nor_init(struct platform_device *pdev,
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unsigned long base, uint32_t bank, uint32_t width);
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extern void __init fsmc_init_board_info(struct platform_device *pdev,
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struct mtd_partition *partitions, unsigned int nr_partitions,
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unsigned int width);
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#endif /* __MTD_FSMC_H */
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