irqchip: RISC-V per-HART local interrupt controller driver
The RISC-V per-HART local interrupt controller manages software interrupts, timer interrupts, external interrupts (which are routed via the platform level interrupt controller) and other per-HART local interrupts. We add a driver for the RISC-V local interrupt controller, which eventually replaces the RISC-V architecture code, allowing for a better split between arch code and drivers. The driver is compliant with RISC-V Hart-Level Interrupt Controller DT bindings located at: Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> [Palmer: Cleaned up warnings] Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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Palmer Dabbelt

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@@ -102,6 +102,7 @@ enum cpuhp_state {
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CPUHP_AP_IRQ_ARMADA_XP_STARTING,
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CPUHP_AP_IRQ_BCM2836_STARTING,
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CPUHP_AP_IRQ_MIPS_GIC_STARTING,
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CPUHP_AP_IRQ_RISCV_STARTING,
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CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
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CPUHP_AP_ARM_MVEBU_COHERENCY,
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CPUHP_AP_MICROCODE_LOADER,
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