Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (37 commits) PCI: merge almost all of pci_32.h and pci_64.h together PCI: X86: Introduce and enable PCI domain support PCI: Add 'nodomains' boot option, and pci_domains_supported global PCI: modify PCI bridge control ISA flag for clarity PCI: use _CRS for PCI resource allocation PCI: avoid P2P prefetch window for expansion ROMs PCI: skip ISA ioresource alignment on some systems PCI: remove transparent bridge sizing pci: write file size to inode on proc bus file write pci: use size stored in proc_dir_entry for proc bus files pci: implement "pci=noaer" PCI: fix IDE legacy mode resources MSI: Use correct data offset for 32-bit MSI in read_msi_msg() PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID code PCI: i386: Compaq EVO N800c needs PCI bus renumbering PCI: Remove no longer correct documentation regarding MSI vector assignment PCI: re-enable onboard sound on "MSI K8T Neo2-FIR" PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for read ...
This commit is contained in:
Linus Torvalds
@@ -68,6 +68,9 @@ size and dma_handle must all be the same as those passed into the
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consistent allocate. cpu_addr must be the virtual address returned by
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the consistent allocate.
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Note that unlike their sibling allocation calls, these routines
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may only be called with IRQs enabled.
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Part Ib - Using small dma-coherent buffers
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------------------------------------------
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@@ -241,68 +241,7 @@ address space of the MSI-X table/MSI-X PBA. Otherwise, the PCI subsystem
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will fail enabling MSI-X on its hardware device when it calls the function
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pci_enable_msix().
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5.3.2 Handling MSI-X allocation
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Determining the number of MSI-X vectors allocated to a function is
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dependent on the number of MSI capable devices and MSI-X capable
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devices populated in the system. The policy of allocating MSI-X
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vectors to a function is defined as the following:
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#of MSI-X vectors allocated to a function = (x - y)/z where
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x = The number of available PCI vector resources by the time
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the device driver calls pci_enable_msix(). The PCI vector
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resources is the sum of the number of unassigned vectors
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(new) and the number of released vectors when any MSI/MSI-X
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device driver switches its hardware device back to a legacy
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mode or is hot-removed. The number of unassigned vectors
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may exclude some vectors reserved, as defined in parameter
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NR_HP_RESERVED_VECTORS, for the case where the system is
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capable of supporting hot-add/hot-remove operations. Users
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may change the value defined in NR_HR_RESERVED_VECTORS to
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meet their specific needs.
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y = The number of MSI capable devices populated in the system.
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This policy ensures that each MSI capable device has its
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vector reserved to avoid the case where some MSI-X capable
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drivers may attempt to claim all available vector resources.
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z = The number of MSI-X capable devices populated in the system.
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This policy ensures that maximum (x - y) is distributed
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evenly among MSI-X capable devices.
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Note that the PCI subsystem scans y and z during a bus enumeration.
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When the PCI subsystem completes configuring MSI/MSI-X capability
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structure of a device as requested by its device driver, y/z is
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decremented accordingly.
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5.3.3 Handling MSI-X shortages
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For the case where fewer MSI-X vectors are allocated to a function
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than requested, the function pci_enable_msix() will return the
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maximum number of MSI-X vectors available to the caller. A device
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driver may re-send its request with fewer or equal vectors indicated
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in the return. For example, if a device driver requests 5 vectors, but
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the number of available vectors is 3 vectors, a value of 3 will be
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returned as a result of pci_enable_msix() call. A function could be
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designed for its driver to use only 3 MSI-X table entries as
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different combinations as ABC--, A-B-C, A--CB, etc. Note that this
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patch does not support multiple entries with the same vector. Such
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attempt by a device driver to use 5 MSI-X table entries with 3 vectors
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as ABBCC, AABCC, BCCBA, etc will result as a failure by the function
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pci_enable_msix(). Below are the reasons why supporting multiple
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entries with the same vector is an undesirable solution.
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- The PCI subsystem cannot determine the entry that
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generated the message to mask/unmask MSI while handling
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software driver ISR. Attempting to walk through all MSI-X
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table entries (2048 max) to mask/unmask any match vector
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is an undesirable solution.
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- Walking through all MSI-X table entries (2048 max) to handle
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SMP affinity of any match vector is an undesirable solution.
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5.3.4 API pci_enable_msix
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5.3.2 API pci_enable_msix
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int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
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@@ -339,7 +278,7 @@ a failure. This failure may be a result of duplicate entries
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specified in second argument, or a result of no available vector,
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or a result of failing to initialize MSI-X table entries.
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5.3.5 API pci_disable_msix
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5.3.3 API pci_disable_msix
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void pci_disable_msix(struct pci_dev *dev)
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@@ -349,7 +288,7 @@ always call free_irq() on all MSI-X vectors it has done request_irq()
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on before calling this API. Failure to do so results in a BUG_ON() and
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a device will be left with MSI-X enabled and leaks its vectors.
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5.3.6 MSI-X mode vs. legacy mode diagram
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5.3.4 MSI-X mode vs. legacy mode diagram
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The below diagram shows the events which switch the interrupt
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mode on the MSI-X capable device function between MSI-X mode and
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@@ -407,7 +346,7 @@ between MSI mod MSI-X mode during a run-time.
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MSI/MSI-X support requires support from both system hardware and
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individual hardware device functions.
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5.5.1 System hardware support
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5.5.1 Required x86 hardware support
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Since the target of MSI address is the local APIC CPU, enabling
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MSI/MSI-X support in the Linux kernel is dependent on whether existing
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@@ -68,6 +68,7 @@ parameter is applicable:
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PARIDE The ParIDE (parallel port IDE) subsystem is enabled.
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PARISC The PA-RISC architecture is enabled.
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PCI PCI bus support is enabled.
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PCIE PCI Express support is enabled.
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PCMCIA The PCMCIA subsystem is enabled.
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PNP Plug & Play support is enabled.
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PPC PowerPC architecture is enabled.
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@@ -1277,6 +1278,11 @@ and is between 256 and 4096 characters. It is defined in the file
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Mechanism 1.
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conf2 [X86-32] Force use of PCI Configuration
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Mechanism 2.
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noaer [PCIE] If the PCIEAER kernel config parameter is
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enabled, this kernel boot option can be used to
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disable the use of PCIE advanced error reporting.
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nodomains [PCI] Disable support for multiple PCI
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root domains (aka PCI segments, in ACPI-speak).
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nommconf [X86-32,X86_64] Disable use of MMCONFIG for PCI
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Configuration
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nomsi [MSI] If the PCI_MSI kernel config parameter is
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@@ -1321,6 +1327,8 @@ and is between 256 and 4096 characters. It is defined in the file
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IRQ routing is enabled.
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noacpi [X86-32] Do not use ACPI for IRQ routing
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or for PCI scanning.
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use_crs [X86-32] Use _CRS for PCI resource
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allocation.
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routeirq Do IRQ routing for all PCI devices.
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This is normally done in pci_enable_device(),
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so this option is a temporary workaround
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