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net/mlx5e: Turn on HW tunnel offload in all TIRs

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Hardware requires that all TIRs that steer traffic to the same RQ
should share identical tunneled_offload_en value.
For that, the tunneled_offload_en bit should be set/unset (according to
the HW capability) for all TIRs', not only the ones dedicated for
tunneled (inner) traffic.

Fixes: 1b223dd391 ("net/mlx5e: Fix checksum handling for non-stripped vlan packets")
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
Tariq Toukan
2019-01-20 11:04:34 +02:00
committed by Saeed Mahameed
parent 7306c274e7
commit 69dad68d1b
4 changed files with 7 additions and 1 deletions
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1
drivers/net/ethernet/mellanox/mlx5/core/en.h
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@@ -240,6 +240,7 @@ struct mlx5e_params {
bool rx_cqe_compress_def; bool rx_cqe_compress_def;
struct net_dim_cq_moder rx_cq_moderation; struct net_dim_cq_moder rx_cq_moderation;
struct net_dim_cq_moder tx_cq_moderation; struct net_dim_cq_moder tx_cq_moderation;
bool tunneled_offload_en;
bool lro_en; bool lro_en;
u8 tx_min_inline_mode; u8 tx_min_inline_mode;
bool vlan_strip_disable; bool vlan_strip_disable;

5
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
View File

@@ -3100,6 +3100,8 @@ static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
MLX5_SET(tirc, tirc, indirect_table, rqtn); MLX5_SET(tirc, tirc, indirect_table, rqtn);
MLX5_SET(tirc, tirc, tunneled_offload_en,
priv->channels.params.tunneled_offload_en);
mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
} }
@@ -3126,7 +3128,6 @@ static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc); mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
&tirc_default_config[tt], tirc, true); &tirc_default_config[tt], tirc, true);
MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
} }
int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc) int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
@@ -4572,6 +4573,8 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
/* RSS */ /* RSS */
mlx5e_build_rss_params(rss_params, params->num_channels); mlx5e_build_rss_params(rss_params, params->num_channels);
params->tunneled_offload_en =
mlx5e_tunnel_inner_ft_supported(mdev);
} }
static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)

1
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
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@@ -1375,6 +1375,7 @@ static void mlx5e_build_rep_params(struct net_device *netdev)
mlx5e_set_rx_cq_mode_params(params, cq_period_mode); mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
params->num_tc = 1; params->num_tc = 1;
params->tunneled_offload_en = false;
mlx5_query_min_inline(mdev, &params->tx_min_inline_mode); mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);

1
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
View File

@@ -68,6 +68,7 @@ static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
params->lro_en = false; params->lro_en = false;
params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN; params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
params->tunneled_offload_en = false;
} }
/* Called directly after IPoIB netdevice was created to initialize SW structs */ /* Called directly after IPoIB netdevice was created to initialize SW structs */