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Merge tag 'arm-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM SoC updates from Arnd Bergmann:
 "One new platform gets added, the Realtek RTD1195, which is an older
  Cortex-a7 based relative of the RTD12xx chips that are already
  supported in arch/arm64. The platform may also be extended to support
  running 32-bit kernels on those 64-bit chips for memory-constrained
  machines.

  In the Renesas shmobile platform, we gain support for "RZ/G1H" or
  R8A7742, an eight-core chip based on Cortex-A15 and Cortex-A7 cores,
  originally released in 2016 as one of the last high-end 32-bit
  designs.

  There is ongoing cleanup for the integrator, tegra, imx, and omap2
  platforms, with integrator getting very close to the goal of having
  zero code in arch/arm/, and omap2 moving more of the chip specifics
  from old board code into device tree files.

  The Versatile Express platform is made more modular, with built-in
  drivers now becoming loadable modules. This is part of a greater
  effort for the Android OS to have a common kernel binary for all
  platforms and any platform specific code in loadable modules.

  The PXA platform drops support for Compulab's pxa2xx boards that had
  rather unusual flash and PCI drivers but no known users remaining. All
  device drivers specific to those boards can now get removed as well.

  Across platforms, there is ongoing cleanup, with Geert and Rob
  revisiting some a lot of Kconfig options"

* tag 'arm-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits)
  ARM: omap2: fix omap5_realtime_timer_init definition
  ARM: zynq: Don't select CONFIG_ICST
  ARM: OMAP2+: Fix regression for using local timer on non-SMP SoCs
  clk: versatile: Fix kconfig dependency on COMMON_CLK_VERSATILE
  ARM: davinci: fix build failure without I2C
  power: reset: vexpress: fix build issue
  power: vexpress: cleanup: use builtin_platform_driver
  power: vexpress: add suppress_bind_attrs to true
  Revert "ARM: vexpress: Don't select VEXPRESS_CONFIG"
  MAINTAINERS: pxa: remove Compulab arm/pxa support
  ARM: pxa: remove Compulab pxa2xx boards
  bus: arm-integrator-lm: Fix return value check in integrator_ap_lm_probe()
  soc: imx: move cpu code to drivers/soc/imx
  ARM: imx: move cpu definitions into a header
  ARM: imx: use device_initcall for imx_soc_device_init
  ARM: imx: pcm037: make pcm970_sja1000_platform_data static
  bus: ti-sysc: Timers no longer need legacy quirk handling
  ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter
  ARM: dts: Configure system timers for omap2
  ARM: dts: Configure system timers for ti81xx
  ...
This commit is contained in:
Linus Torvalds
2020-06-04 19:47:11 -07:00
parent 587f17018a d2353bad2c
commit 694b5a5d31
145 changed files with 1635 additions and 6247 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@@ -330,9 +330,8 @@
};
};
target-module@31000 { /* 0x44e31000, ap 25 40.0 */
timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -1117,9 +1116,8 @@
};
};
target-module@40000 { /* 0x48040000, ap 22 1e.0 */
timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;

20
arch/arm/boot/dts/am33xx.dtsi
View File

@@ -619,3 +619,23 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

24
arch/arm/boot/dts/am3517.dtsi
View File

@@ -169,5 +169,25 @@
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
#include "am35xx-clocks.dtsi"
#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&sys_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};

20
arch/arm/boot/dts/am4372.dtsi
View File

@@ -553,3 +553,23 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

7
arch/arm/boot/dts/am437x-l4.dtsi
View File

@@ -328,9 +328,8 @@
};
};
target-module@31000 { /* 0x44e31000, ap 24 40.0 */
timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -450,7 +449,6 @@
target-module@86000 { /* 0x44e86000, ap 40 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x86000 0x4>,
<0x86004 0x4>;
reg-names = "rev", "sysc";
@@ -868,9 +866,8 @@
};
};
target-module@40000 { /* 0x48040000, ap 18 1e.0 */
timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;

74
arch/arm/boot/dts/dm814x.dtsi
View File

@@ -308,14 +308,30 @@
ti,hwmods = "mcspi4";
};
timer1: timer@2e000 {
compatible = "ti,dm814-timer";
reg = <0x2e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@2e000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&timer1_fck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2e000 0x1000>;
timer1: timer@0 {
compatible = "ti,am335x-timer-1ms";
reg = <0x0 0x400>;
interrupts = <67>;
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
};
uart1: uart@20000 {
@@ -348,13 +364,29 @@
dma-names = "tx", "rx";
};
timer2: timer@40000 {
compatible = "ti,dm814-timer";
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
timer2_target: target-module@40000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&timer2_fck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000 0x1000>;
timer2: timer@0 {
compatible = "ti,dm814-timer";
reg = <0 0x1000>;
interrupts = <68>;
clocks = <&timer2_fck>;
clock-names = "fck";
};
};
timer3: timer@42000 {
@@ -735,3 +767,23 @@
};
#include "dm814x-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&devosc_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&devosc_ck>;
};
};

78
arch/arm/boot/dts/dm816x.dtsi
View File

@@ -440,23 +440,55 @@
dma-names = "tx", "rx";
};
timer1: timer@4802e000 {
compatible = "ti,dm816-timer";
reg = <0x4802e000 0x2000>;
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
timer1_target: target-module@4802e000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x4802e000 0x4>,
<0x4802e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4802e000 0x1000>;
timer1: timer@0 {
compatible = "ti,dm816-timer";
reg = <0 0x1000>;
interrupts = <67>;
ti,timer-alwon;
clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
};
};
timer2: timer@48040000 {
compatible = "ti,dm816-timer";
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
timer2_target: target-module@48040000 {
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x48040000 0x4>,
<0x48040010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48040000 0x1000>;
timer2: timer@0 {
compatible = "ti,dm816-timer";
reg = <0 0x1000>;
interrupts = <68>;
clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
};
};
timer3: timer@48042000 {
@@ -642,3 +674,23 @@
};
#include "dm816x-clocks.dtsi"
/* Preferred always-on timer for clocksource */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer1_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&timer2_fck>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

7
arch/arm/boot/dts/dra7-l4.dtsi
View File

@@ -1143,7 +1143,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -1171,7 +1170,6 @@
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1199,7 +1197,6 @@
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -4295,7 +4292,6 @@
target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -4430,9 +4426,8 @@
};
};
target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";

10
arch/arm/boot/dts/dra7.dtsi
View File

@@ -1044,3 +1044,13 @@
reg = <0x1c00 0x60>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_32k_ck>;
};
};

31
arch/arm/boot/dts/omap2.dtsi
View File

@@ -201,11 +201,32 @@
clock-frequency = <48000000>;
};
timer2: timer@4802a000 {
compatible = "ti,omap2420-timer";
reg = <0x4802a000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
timer2_target: target-module@4802a000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x4802a000 0x4>,
<0x4802a010 0x4>,
<0x4802a014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt2_fck>, <&gpt2_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4802a000 0x1000>;
timer2: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <38>;
};
};
timer3: timer@48078000 {

68
arch/arm/boot/dts/omap2420.dtsi
View File

@@ -68,10 +68,23 @@
};
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&func_32k_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0 0x20>;
};
};
};
@@ -194,12 +207,33 @@
};
};
timer1: timer@48028000 {
compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@48028000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48028000 0x4>,
<0x48028010 0x4>,
<0x48028014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48028000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <37>;
ti,timer-alwon;
};
};
wd_timer2: wdt@48022000 {
@@ -218,5 +252,15 @@
compatible = "ti,omap2420-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2420-clocks.dtsi"
#include "omap24xx-clocks.dtsi"
#include "omap2420-clocks.dtsi"
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&func_32k_ck>;
};
};

68
arch/arm/boot/dts/omap2430.dtsi
View File

@@ -81,10 +81,23 @@
};
};
counter32k: counter@20000 {
compatible = "ti,omap-counter32k";
reg = <0x20000 0x20>;
ti,hwmods = "counter_32k";
target-module@20000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x20000 0x4>,
<0x20004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&func_32k_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0 0x20>;
};
};
};
@@ -277,12 +290,33 @@
};
};
timer1: timer@49018000 {
compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@49018000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x49018000 0x4>,
<0x49018010 0x4>,
<0x49018014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49018000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap2420-timer";
reg = <0 0x400>;
interrupts = <37>;
ti,timer-alwon;
};
};
mcspi3: spi@480b8000 {
@@ -321,5 +355,15 @@
compatible = "ti,omap2430-i2c";
};
/include/ "omap24xx-clocks.dtsi"
/include/ "omap2430-clocks.dtsi"
#include "omap24xx-clocks.dtsi"
#include "omap2430-clocks.dtsi"
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&func_32k_ck>;
};
};

33
arch/arm/boot/dts/omap3-beagle.dts
View File

@@ -304,6 +304,39 @@
phys = <0 &hsusb2_phy>;
};
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */

33
arch/arm/boot/dts/omap3-devkit8000.dts
View File

@@ -14,3 +14,36 @@
display2 = &tv0;
};
};
/* Unusable as clocksource because of unreliable oscillator */
&counter32k {
status = "disabled";
};
/* Unusable as clockevent because if unreliable oscillator, allow to idle */
&timer1_target {
/delete-property/ti,no-reset-on-init;
/delete-property/ti,no-idle;
timer@0 {
/delete-property/ti,timer-alwon;
};
};
/* Preferred always-on timer for clocksource */
&timer12_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
/* Always clocked by secure_32k_fck */
};
};
/* Preferred timer for clockevent */
&timer2_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt2_fck>;
assigned-clock-parents = <&sys_ck>;
};
};

134
arch/arm/boot/dts/omap3.dtsi
View File

@@ -193,10 +193,23 @@
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
ti,hwmods = "counter_32k";
target-module@48320000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x48320000 0x4>,
<0x48320004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48320000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0x0 0x20>;
};
};
intc: interrupt-controller@48200000 {
@@ -637,19 +650,63 @@
dma-names = "rx";
};
timer1: timer@48318000 {
compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
timer1_target: target-module@48318000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48318000 0x4>,
<0x48318010 0x4>,
<0x48318014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt1_fck>, <&gpt1_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48318000 0x1000>;
timer1: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0x0 0x80>;
clocks = <&gpt1_fck>;
clock-names = "fck";
interrupts = <37>;
ti,timer-alwon;
};
};
timer2: timer@49032000 {
compatible = "ti,omap3430-timer";
reg = <0x49032000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
timer2_target: target-module@49032000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x49032000 0x4>,
<0x49032010 0x4>,
<0x49032014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt2_fck>, <&gpt2_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49032000 0x1000>;
timer2: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0 0x400>;
interrupts = <38>;
};
};
timer3: timer@49034000 {
@@ -723,13 +780,34 @@
ti,timer-pwm;
};
timer12: timer@48304000 {
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12";
ti,timer-alwon;
ti,timer-secure;
timer12_target: target-module@48304000 {
compatible = "ti,sysc-omap2-timer", "ti,sysc";
reg = <0x48304000 0x4>,
<0x48304010 0x4>,
<0x48304014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&gpt12_fck>, <&gpt12_ick>;
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x48304000 0x1000>;
timer12: timer@0 {
compatible = "ti,omap3430-timer";
reg = <0 0x400>;
interrupts = <95>;
ti,timer-alwon;
ti,timer-secure;
};
};
usbhstll: usbhstll@48062000 {
@@ -886,4 +964,14 @@
};
};
/include/ "omap3xxx-clocks.dtsi"
#include "omap3xxx-clocks.dtsi"
/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&gpt1_fck>;
assigned-clock-parents = <&omap_32k_fck>;
};
};

4
arch/arm/boot/dts/omap4-l4.dtsi
View File

@@ -974,7 +974,6 @@
target-module@4000 { /* 0x4a304000, ap 17 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -1139,9 +1138,8 @@
};
};
target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>,
<0x8014 0x4>;

10
arch/arm/boot/dts/omap4.dtsi
View File

@@ -655,3 +655,13 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin_ck>;
};
};

4
arch/arm/boot/dts/omap5-l4.dtsi
View File

@@ -2150,7 +2150,6 @@
target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -2336,9 +2335,8 @@
};
};
target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";

10
arch/arm/boot/dts/omap5.dtsi
View File

@@ -581,3 +581,13 @@
#reset-cells = <1>;
};
};
/* Preferred always-on timer for clockevent */
&timer1_target {
ti,no-reset-on-init;
ti,no-idle;
timer@0 {
assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
assigned-clock-parents = <&sys_32k_ck>;
};
};