Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.
The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.
I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.
Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.
Summary:
Core changes:
- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- switch meson driver to get the GPIO ranges from the device tree.
- input schmitt trigger support on the Rockchip driver.
- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- name the Qualcomm QDF2xxx GPIO lines.
- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.
- pad retention support for the Samsung Exynos 5433.
- handle suspend-to-ram in the AT91-pio4 driver.
- pin configuration support in the Aspeed driver.
Cleanups:
- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"
* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...
This commit is contained in:
Linus Torvalds
@@ -5,6 +5,7 @@ reading the gpio latch register.
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This node must be a subnode of the node exposing the register address
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of the GPIO block where the gpio latch is located.
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See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
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Required properties:
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- compatible : shall be one of the following:
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@@ -16,9 +17,9 @@ Optional properties:
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output names ("xtal")
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Example:
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gpio1: gpio@13800 {
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compatible = "marvell,armada-3700-gpio", "syscon", "simple-mfd";
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reg = <0x13800 0x1000>;
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pinctrl_nb: pinctrl-nb@13800 {
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compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
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reg = <0x13800 0x100>, <0x13C00 0x20>;
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xtalclk: xtal-clk {
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compatible = "marvell,armada-3700-xtal-clock";
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@@ -23,7 +23,8 @@ Required properties:
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"allwinner,sun8i-h3-pinctrl"
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"allwinner,sun8i-h3-r-pinctrl"
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"allwinner,sun50i-a64-pinctrl"
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"allwinner,sun50i-h5-r-pinctrl"
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"allwinner,sun50i-a64-r-pinctrl"
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"allwinner,sun50i-h5-pinctrl"
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"nextthing,gr8-pinctrl"
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- reg: Should contain the register physical address and length for the
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@@ -4,7 +4,7 @@ The AT91 Pinmux Controller, enables the IC
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to share one PAD to several functional blocks. The sharing is done by
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multiplexing the PAD input/output signals. For each PAD there are up to
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8 muxing options (called periph modes). Since different modules require
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different PAD settings (like pull up, keeper, etc) the contoller controls
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different PAD settings (like pull up, keeper, etc) the controller controls
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also the PAD settings parameters.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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@@ -0,0 +1,85 @@
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Axis ARTPEC-6 Pin Controller
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Required properties:
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- compatible: "axis,artpec6-pinctrl".
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- reg: Should contain the register physical address and length for the pin
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controller.
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A pinctrl node should contain at least one subnode representing the pinctrl
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groups available on the machine. Each subnode will list the mux function
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required and what pin group it will use. Each subnode will also configure the
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drive strength and bias pullup of the pin group. If either of these options is
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not set, its actual value will be unspecified.
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Required subnode-properties:
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- function: Function to mux.
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- groups: Name of the pin group to use for the function above.
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Available functions and groups (function: group0, group1...):
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gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
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i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
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spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
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uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
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cpuclkout: cpuclkoutgrp0
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udlclkout: udlclkoutgrp0
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i2c1: i2c1grp0
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i2c2: i2c2grp0
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i2c3: i2c3grp0
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i2s0: i2s0grp0
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i2s1: i2s1grp0
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i2srefclk: i2srefclkgrp0
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spi0: spi0grp0
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spi1: spi1grp0
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pciedebug: pciedebuggrp0
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uart0: uart0grp0, uart0grp1
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uart1: uart1grp0
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uart2: uart2grp0, uart2grp1
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uart3: uart3grp0
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uart4: uart4grp0
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uart5: uart5grp0
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nand: nandgrp0
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sdio0: sdio0grp0
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sdio1: sdio1grp0
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ethernet: ethernetgrp0
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Optional subnode-properties (see pinctrl-bindings.txt):
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- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
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- bias-pull-up
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- bias-disable
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Examples:
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pinctrl@f801d000 {
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compatible = "axis,artpec6-pinctrl";
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reg = <0xf801d000 0x400>;
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pinctrl_uart0: uart0grp {
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function = "uart0";
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groups = "uart0grp0";
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drive-strength = <4>;
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bias-pull-up;
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};
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pinctrl_uart3: uart3grp {
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function = "uart3";
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groups = "uart3grp0";
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};
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};
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uart0: uart@f8036000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8036000 0x1000>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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};
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uart3: uart@f8039000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8039000 0x1000>;
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interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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};
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@@ -0,0 +1,183 @@
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* Marvell Armada 37xx SoC pin and gpio controller
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Each Armada 37xx SoC come with two pin and gpio controller one for the
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south bridge and the other for the north bridge.
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Inside this set of register the gpio latch allows exposing some
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configuration of the SoC and especially the clock frequency of the
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xtal. Hence, this node is a represent as syscon allowing sharing the
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register between multiple hardware block.
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GPIO and pin controller:
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------------------------
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Main node:
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Refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning
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of the phrase "pin configuration node".
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Required properties for pinctrl driver:
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- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
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for the south bridge
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"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
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for the north bridge
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- reg: The first set of register are for pinctrl/gpio and the second
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set for the interrupt controller
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- interrupts: list of the interrupt use by the gpio
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Available groups and functions for the North bridge:
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group: jtag
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- pins 20-24
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- functions jtag, gpio
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group sdio0
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- pins 8-10
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- functions sdio, gpio
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group emmc_nb
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- pins 27-35
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- functions emmc, gpio
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group pwm0
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- pin 11 (GPIO1-11)
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- functions pwm, gpio
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group pwm1
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- pin 12
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- functions pwm, gpio
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group pwm2
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- pin 13
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- functions pwm, gpio
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group pwm3
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- pin 14
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- functions pwm, gpio
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group pmic1
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- pin 17
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- functions pmic, gpio
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group pmic0
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- pin 16
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- functions pmic, gpio
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group i2c2
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- pins 2-3
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- functions i2c, gpio
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group i2c1
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- pins 0-1
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- functions i2c, gpio
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group spi_cs1
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- pin 17
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- functions spi, gpio
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group spi_cs2
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- pin 18
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- functions spi, gpio
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group spi_cs3
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- pin 19
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- functions spi, gpio
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group onewire
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- pin 4
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- functions onewire, gpio
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group uart1
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- pins 25-26
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- functions uart, gpio
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group spi_quad
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- pins 15-16
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- functions spi, gpio
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group uart_2
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- pins 9-10
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- functions uart, gpio
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Available groups and functions for the South bridge:
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group usb32_drvvbus0
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- pin 36
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- functions drvbus, gpio
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group usb2_drvvbus1
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- pin 37
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- functions drvbus, gpio
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group sdio_sb
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- pins 60-64
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- functions sdio, gpio
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group rgmii
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- pins 42-55
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- functions mii, gpio
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group pcie1
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- pins 39-40
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- functions pcie, gpio
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group ptp
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- pins 56-58
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- functions ptp, gpio
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group ptp_clk
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- pin 57
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- functions ptp, mii
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group ptp_trig
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- pin 58
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- functions ptp, mii
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group mii_col
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- pin 59
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- functions mii, mii_err
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GPIO subnode:
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Please refer to gpio.txt in this directory for details of gpio-ranges property
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and the common GPIO bindings used by client devices.
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Required properties for gpio driver under the gpio subnode:
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- interrupts: List of interrupt specifier for the controllers interrupt.
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- gpio-controller: Marks the device node as a gpio controller.
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- #gpio-cells: Should be 2. The first cell is the GPIO number and the
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second cell specifies GPIO flags, as defined in
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<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
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GPIO_ACTIVE_LOW flags are supported.
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- gpio-ranges: Range of pins managed by the GPIO controller.
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Xtal Clock bindings for Marvell Armada 37xx SoCs
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------------------------------------------------
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see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
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Example:
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pinctrl_sb: pinctrl-sb@18800 {
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compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 29>;
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gpio-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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rgmii_pins: mii-pins {
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groups = "rgmii";
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function = "mii";
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};
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};
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@@ -34,13 +34,28 @@ Documentation/devicetree/bindings/mfd/syscon.txt
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Subnode Format
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||||
==============
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||||
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The required properties of child nodes are (as defined in pinctrl-bindings):
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- function
|
||||
- groups
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||||
The required properties of pinmux child nodes are:
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||||
- function: the mux function to select
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||||
- groups : the list of groups to select with this function
|
||||
|
||||
Each function has only one associated pin group. Each group is named by its
|
||||
function. The following values for the function and groups properties are
|
||||
supported:
|
||||
Required properties of pinconf child nodes are:
|
||||
- groups: A list of groups to select (either this or "pins" must be
|
||||
specified)
|
||||
- pins : A list of ball names as strings, eg "D14" (either this or "groups"
|
||||
must be specified)
|
||||
|
||||
Optional properties of pinconf child nodes are:
|
||||
- bias-disable : disable any pin bias
|
||||
- bias-pull-down: pull down the pin
|
||||
- drive-strength: sink or source at most X mA
|
||||
|
||||
Definitions are as specified in
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any
|
||||
further limitations as described above.
|
||||
|
||||
For pinmux, each mux function has only one associated pin group. Each group is
|
||||
named by its function. The following values for the function and groups
|
||||
properties are supported:
|
||||
|
||||
aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
|
||||
|
||||
@@ -90,6 +105,11 @@ syscon: scu@1e6e2000 {
|
||||
function = "I2C3";
|
||||
groups = "I2C3";
|
||||
};
|
||||
|
||||
pinctrl_gpioh0_unbiased_default: gpioh0 {
|
||||
pins = "A8";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -110,6 +130,11 @@ ahb {
|
||||
function = "I2C3";
|
||||
groups = "I2C3";
|
||||
};
|
||||
|
||||
pinctrl_gpioh0_unbiased_default: gpioh0 {
|
||||
pins = "A18";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -143,6 +168,3 @@ ahb {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices.
|
||||
|
||||
@@ -162,8 +162,8 @@ state_2_node_a {
|
||||
pins = "mfio29", "mfio30";
|
||||
};
|
||||
|
||||
Optionally an altenative binding can be used if more suitable depending on the
|
||||
pin controller hardware. For hardaware where there is a large number of identical
|
||||
Optionally an alternative binding can be used if more suitable depending on the
|
||||
pin controller hardware. For hardware where there is a large number of identical
|
||||
pin controller instances, naming each pin and function can easily become
|
||||
unmaintainable. This is especially the case if the same controller is used for
|
||||
different pins and functions depending on the SoC revision and packaging.
|
||||
@@ -198,6 +198,28 @@ registers, and must not be a virtual index of pin instances. The reason for
|
||||
this is to avoid mapping of the index in the dts files and the pin controller
|
||||
driver as it can change.
|
||||
|
||||
For hardware where pin multiplexing configurations have to be specified for
|
||||
each single pin the number of required sub-nodes containing "pin" and
|
||||
"function" properties can quickly escalate and become hard to write and
|
||||
maintain.
|
||||
|
||||
For cases like this, the pin controller driver may use the pinmux helper
|
||||
property, where the pin identifier is packed with mux configuration settings
|
||||
in a single integer.
|
||||
|
||||
The pinmux property accepts an array of integers, each of them describing
|
||||
a single pin multiplexing configuration.
|
||||
|
||||
pincontroller {
|
||||
state_0_node_a {
|
||||
pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ...;
|
||||
};
|
||||
};
|
||||
|
||||
Each individual pin controller driver bindings documentation shall specify
|
||||
how those values (pin IDs and pin multiplexing configuration) are defined and
|
||||
assembled together.
|
||||
|
||||
== Generic pin configuration node content ==
|
||||
|
||||
Many data items that are represented in a pin configuration node are common
|
||||
@@ -210,18 +232,22 @@ structure of the DT nodes that contain these properties.
|
||||
Supported generic properties are:
|
||||
|
||||
pins - the list of pins that properties in the node
|
||||
apply to (either this or "group" has to be
|
||||
apply to (either this, "group" or "pinmux" has to be
|
||||
specified)
|
||||
group - the group to apply the properties to, if the driver
|
||||
supports configuration of whole groups rather than
|
||||
individual pins (either this or "pins" has to be
|
||||
specified)
|
||||
individual pins (either this, "pins" or "pinmux" has
|
||||
to be specified)
|
||||
pinmux - the list of numeric pin ids and their mux settings
|
||||
that properties in the node apply to (either this,
|
||||
"pins" or "groups" have to be specified)
|
||||
bias-disable - disable any pin bias
|
||||
bias-high-impedance - high impedance mode ("third-state", "floating")
|
||||
bias-bus-hold - latch weakly
|
||||
bias-pull-up - pull up the pin
|
||||
bias-pull-down - pull down the pin
|
||||
bias-pull-pin-default - use pin-default pull state
|
||||
bi-directional - pin supports simultaneous input/output operations
|
||||
drive-push-pull - drive actively high and low
|
||||
drive-open-drain - drive with open drain
|
||||
drive-open-source - drive with open source
|
||||
@@ -234,6 +260,7 @@ input-debounce - debounce mode with debound time X
|
||||
power-source - select between different power supplies
|
||||
low-power-enable - enable low power mode
|
||||
low-power-disable - disable low power mode
|
||||
output-enable - enable output on pin regardless of output value
|
||||
output-low - set the pin to output mode with low level
|
||||
output-high - set the pin to output mode with high level
|
||||
slew-rate - set the slew rate
|
||||
@@ -258,6 +285,12 @@ state_2_node_a {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
state_3_node_a {
|
||||
mux {
|
||||
pinmux = <GPIOx_PINm_MUXn>, <GPIOx_PINj_MUXk)>;
|
||||
input-enable;
|
||||
};
|
||||
};
|
||||
|
||||
Some of the generic properties take arguments. For those that do, the
|
||||
arguments are described below.
|
||||
@@ -266,6 +299,11 @@ arguments are described below.
|
||||
binding for the hardware defines:
|
||||
- Whether the entries are integers or strings, and their meaning.
|
||||
|
||||
- pinmux takes a list of pin IDs and mux settings as required argument. The
|
||||
specific bindings for the hardware defines:
|
||||
- How pin IDs and mux settings are defined and assembled together in a single
|
||||
integer.
|
||||
|
||||
- bias-pull-up, -down and -pin-default take as optional argument on hardware
|
||||
supporting it the pull strength in Ohm. bias-disable will disable the pull.
|
||||
|
||||
|
||||
@@ -19,11 +19,18 @@ The pins are grouped into up to 5 individual pin banks which need to be
|
||||
defined as gpio sub-nodes of the pinmux controller.
|
||||
|
||||
Required properties for iomux controller:
|
||||
- compatible: one of "rockchip,rk1108-pinctrl", "rockchip,rk2928-pinctrl"
|
||||
"rockchip,rk3066a-pinctrl", "rockchip,rk3066b-pinctrl"
|
||||
"rockchip,rk3188-pinctrl", "rockchip,rk3228-pinctrl"
|
||||
"rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
|
||||
"rockchip,rk3399-pinctrl"
|
||||
- compatible: should be
|
||||
"rockchip,rv1108-pinctrl": for Rockchip RV1108
|
||||
"rockchip,rk2928-pinctrl": for Rockchip RK2928
|
||||
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
|
||||
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
|
||||
"rockchip,rk3188-pinctrl": for Rockchip RK3188
|
||||
"rockchip,rk3228-pinctrl": for Rockchip RK3228
|
||||
"rockchip,rk3288-pinctrl": for Rockchip RK3288
|
||||
"rockchip,rk3328-pinctrl": for Rockchip RK3328
|
||||
"rockchip,rk3368-pinctrl": for Rockchip RK3368
|
||||
"rockchip,rk3399-pinctrl": for Rockchip RK3399
|
||||
|
||||
- rockchip,grf: phandle referencing a syscon providing the
|
||||
"general register files"
|
||||
|
||||
|
||||
@@ -9,6 +9,7 @@ Pin controller node:
|
||||
Required properies:
|
||||
- compatible: value should be one of the following:
|
||||
"st,stm32f429-pinctrl"
|
||||
"st,stm32f469-pinctrl"
|
||||
"st,stm32f746-pinctrl"
|
||||
"st,stm32h743-pinctrl"
|
||||
- #address-cells: The value of this property must be 1
|
||||
@@ -38,8 +39,6 @@ Optional properties:
|
||||
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
|
||||
which includes IRQ mux selection register, and the offset of the IRQ mux
|
||||
selection register.
|
||||
- ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
|
||||
than 16).
|
||||
- gpio-ranges: Define a dedicated mapping between a pin-controller and
|
||||
a gpio controller. Format is <&phandle a b c> with:
|
||||
-(phandle): phandle of pin-controller.
|
||||
|
||||
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