sfc: Use generic MDIO functions and definitions
Make use of the newly-added generic MDIO clause 45 support and remove redundant definitions. Add an 'efx_' prefix to the remaining driver-specific MDIO functions and remove arguments which are redundant with efx->mdio.prtad. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ben Hutchings
committed by
David S. Miller
David S. Miller
parent
1b1c2e9510
commit
68e7f45e11
@@ -17,7 +17,7 @@
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#include "boards.h"
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#include "workarounds.h"
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unsigned mdio_id_oui(u32 id)
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unsigned efx_mdio_id_oui(u32 id)
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{
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unsigned oui = 0;
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int i;
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@@ -32,52 +32,45 @@ unsigned mdio_id_oui(u32 id)
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return oui;
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}
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int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
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int efx_mdio_reset_mmd(struct efx_nic *port, int mmd,
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int spins, int spintime)
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{
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u32 ctrl;
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int phy_id = port->mii.phy_id;
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/* Catch callers passing values in the wrong units (or just silly) */
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EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
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mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
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(1 << MDIO_MMDREG_CTRL1_RESET_LBN));
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efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
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/* Wait for the reset bit to clear. */
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do {
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msleep(spintime);
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ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
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ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1);
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spins--;
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} while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
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} while (spins && (ctrl & MDIO_CTRL1_RESET));
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return spins ? spins : -ETIMEDOUT;
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}
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static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
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int fault_fatal)
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static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd, int fault_fatal)
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{
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int status;
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int phy_id = efx->mii.phy_id;
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if (LOOPBACK_INTERNAL(efx))
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return 0;
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if (mmd != MDIO_MMD_AN) {
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/* Read MMD STATUS2 to check it is responding. */
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status = mdio_clause45_read(efx, phy_id, mmd,
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MDIO_MMDREG_STAT2);
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if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
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((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
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MDIO_MMDREG_STAT2_PRESENT_VAL) {
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status = efx_mdio_read(efx, mmd, MDIO_STAT2);
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if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) {
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EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
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return -EIO;
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}
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}
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/* Read MMD STATUS 1 to check for fault. */
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status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
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if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
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status = efx_mdio_read(efx, mmd, MDIO_STAT1);
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if (status & MDIO_STAT1_FAULT) {
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if (fault_fatal) {
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EFX_ERR(efx, "PHY MMD %d reporting fatal"
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" fault: status %x\n", mmd, status);
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@@ -94,8 +87,7 @@ static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
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#define MDIO45_RESET_TIME 1000 /* ms */
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#define MDIO45_RESET_ITERS 100
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int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
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unsigned int mmd_mask)
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int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask)
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{
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const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
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int tries = MDIO45_RESET_ITERS;
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@@ -109,16 +101,13 @@ int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
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in_reset = 0;
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while (mask) {
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if (mask & 1) {
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stat = mdio_clause45_read(efx,
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efx->mii.phy_id,
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mmd,
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MDIO_MMDREG_CTRL1);
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stat = efx_mdio_read(efx, mmd, MDIO_CTRL1);
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if (stat < 0) {
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EFX_ERR(efx, "failed to read status of"
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" MMD %d\n", mmd);
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return -EIO;
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}
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if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
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if (stat & MDIO_CTRL1_RESET)
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in_reset |= (1 << mmd);
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}
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mask = mask >> 1;
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@@ -137,28 +126,26 @@ int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
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return rc;
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}
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int mdio_clause45_check_mmds(struct efx_nic *efx,
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unsigned int mmd_mask, unsigned int fatal_mask)
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int efx_mdio_check_mmds(struct efx_nic *efx,
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unsigned int mmd_mask, unsigned int fatal_mask)
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{
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int mmd = 0, probe_mmd, devs0, devs1;
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int mmd = 0, probe_mmd, devs1, devs2;
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u32 devices;
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/* Historically we have probed the PHYXS to find out what devices are
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* present,but that doesn't work so well if the PHYXS isn't expected
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* to exist, if so just find the first item in the list supplied. */
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probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
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probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
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__ffs(mmd_mask);
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/* Check all the expected MMDs are present */
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devs0 = mdio_clause45_read(efx, efx->mii.phy_id,
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probe_mmd, MDIO_MMDREG_DEVS0);
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devs1 = mdio_clause45_read(efx, efx->mii.phy_id,
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probe_mmd, MDIO_MMDREG_DEVS1);
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if (devs0 < 0 || devs1 < 0) {
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devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1);
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devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2);
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if (devs1 < 0 || devs2 < 0) {
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EFX_ERR(efx, "failed to read devices present\n");
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return -EIO;
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}
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devices = devs0 | (devs1 << 16);
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devices = devs1 | (devs2 << 16);
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if ((devices & mmd_mask) != mmd_mask) {
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EFX_ERR(efx, "required MMDs not present: got %x, "
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"wanted %x\n", devices, mmd_mask);
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@@ -170,7 +157,7 @@ int mdio_clause45_check_mmds(struct efx_nic *efx,
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while (mmd_mask) {
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if (mmd_mask & 1) {
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int fault_fatal = fatal_mask & 1;
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if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
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if (efx_mdio_check_mmd(efx, mmd, fault_fatal))
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return -EIO;
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}
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mmd_mask = mmd_mask >> 1;
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@@ -181,13 +168,8 @@ int mdio_clause45_check_mmds(struct efx_nic *efx,
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return 0;
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}
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bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
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bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
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{
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int phy_id = efx->mii.phy_id;
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u32 reg;
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bool ok = true;
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int mmd = 0;
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/* If the port is in loopback, then we should only consider a subset
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* of mmd's */
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if (LOOPBACK_INTERNAL(efx))
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@@ -197,241 +179,75 @@ bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
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else if (efx_phy_mode_disabled(efx->phy_mode))
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return false;
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else if (efx->loopback_mode == LOOPBACK_PHYXS)
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mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |
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MDIO_MMDREG_DEVS_PCS |
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MDIO_MMDREG_DEVS_PMAPMD |
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MDIO_MMDREG_DEVS_AN);
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mmd_mask &= ~(MDIO_DEVS_PHYXS |
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MDIO_DEVS_PCS |
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MDIO_DEVS_PMAPMD |
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MDIO_DEVS_AN);
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else if (efx->loopback_mode == LOOPBACK_PCS)
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mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |
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MDIO_MMDREG_DEVS_PMAPMD |
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MDIO_MMDREG_DEVS_AN);
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mmd_mask &= ~(MDIO_DEVS_PCS |
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MDIO_DEVS_PMAPMD |
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MDIO_DEVS_AN);
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else if (efx->loopback_mode == LOOPBACK_PMAPMD)
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mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD |
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MDIO_MMDREG_DEVS_AN);
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mmd_mask &= ~(MDIO_DEVS_PMAPMD |
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MDIO_DEVS_AN);
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if (!mmd_mask) {
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/* Use presence of XGMII faults in leui of link state */
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reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
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MDIO_PHYXS_STATUS2);
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return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));
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}
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while (mmd_mask) {
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if (mmd_mask & 1) {
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/* Double reads because link state is latched, and a
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* read moves the current state into the register */
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reg = mdio_clause45_read(efx, phy_id,
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mmd, MDIO_MMDREG_STAT1);
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reg = mdio_clause45_read(efx, phy_id,
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mmd, MDIO_MMDREG_STAT1);
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ok = ok && (reg & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
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}
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mmd_mask = (mmd_mask >> 1);
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mmd++;
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}
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return ok;
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return mdio45_links_ok(&efx->mdio, mmd_mask);
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}
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void mdio_clause45_transmit_disable(struct efx_nic *efx)
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void efx_mdio_transmit_disable(struct efx_nic *efx)
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{
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mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
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MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN,
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efx->phy_mode & PHY_MODE_TX_DISABLED);
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efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
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MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL,
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efx->phy_mode & PHY_MODE_TX_DISABLED);
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}
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void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
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void efx_mdio_phy_reconfigure(struct efx_nic *efx)
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{
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int phy_id = efx->mii.phy_id;
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mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
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MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN,
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efx->loopback_mode == LOOPBACK_PMAPMD);
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mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS,
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MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
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efx->loopback_mode == LOOPBACK_PCS);
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mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
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MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
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efx->loopback_mode == LOOPBACK_NETWORK);
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efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
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MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
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efx->loopback_mode == LOOPBACK_PMAPMD);
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efx_mdio_set_flag(efx, MDIO_MMD_PCS,
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MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
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efx->loopback_mode == LOOPBACK_PCS);
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efx_mdio_set_flag(efx, MDIO_MMD_PHYXS,
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MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
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efx->loopback_mode == LOOPBACK_NETWORK);
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}
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static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx,
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int lpower, int mmd)
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static void efx_mdio_set_mmd_lpower(struct efx_nic *efx,
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int lpower, int mmd)
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{
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int phy = efx->mii.phy_id;
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int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
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int stat = efx_mdio_read(efx, mmd, MDIO_STAT1);
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EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
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mmd, lpower);
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if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) {
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mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1,
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MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower);
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if (stat & MDIO_STAT1_LPOWERABLE) {
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efx_mdio_set_flag(efx, mmd, MDIO_CTRL1,
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MDIO_CTRL1_LPOWER, lpower);
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}
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}
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void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
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int low_power, unsigned int mmd_mask)
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void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
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int low_power, unsigned int mmd_mask)
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{
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int mmd = 0;
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mmd_mask &= ~MDIO_MMDREG_DEVS_AN;
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mmd_mask &= ~MDIO_DEVS_AN;
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while (mmd_mask) {
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if (mmd_mask & 1)
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mdio_clause45_set_mmd_lpower(efx, low_power, mmd);
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efx_mdio_set_mmd_lpower(efx, low_power, mmd);
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mmd_mask = (mmd_mask >> 1);
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mmd++;
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}
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}
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static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr)
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{
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int phy_id = efx->mii.phy_id;
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u32 result = 0;
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int reg;
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reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, addr);
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if (reg & ADVERTISE_10HALF)
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result |= ADVERTISED_10baseT_Half;
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if (reg & ADVERTISE_10FULL)
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result |= ADVERTISED_10baseT_Full;
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if (reg & ADVERTISE_100HALF)
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result |= ADVERTISED_100baseT_Half;
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if (reg & ADVERTISE_100FULL)
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result |= ADVERTISED_100baseT_Full;
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return result;
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}
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/**
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* mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
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* @efx: Efx NIC
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* @ecmd: Buffer for settings
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*
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* On return the 'port', 'speed', 'supported' and 'advertising' fields of
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* ecmd have been filled out.
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*/
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void mdio_clause45_get_settings(struct efx_nic *efx,
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struct ethtool_cmd *ecmd)
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{
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mdio_clause45_get_settings_ext(efx, ecmd, 0, 0);
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}
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/**
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* mdio_clause45_get_settings_ext - Read (some of) the PHY settings over MDIO.
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* @efx: Efx NIC
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* @ecmd: Buffer for settings
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* @xnp: Advertised Extended Next Page state
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* @xnp_lpa: Link Partner's advertised XNP state
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*
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* On return the 'port', 'speed', 'supported' and 'advertising' fields of
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* ecmd have been filled out.
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*/
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void mdio_clause45_get_settings_ext(struct efx_nic *efx,
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struct ethtool_cmd *ecmd,
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u32 npage_adv, u32 npage_lpa)
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{
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int phy_id = efx->mii.phy_id;
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int reg;
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ecmd->transceiver = XCVR_INTERNAL;
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ecmd->phy_address = phy_id;
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reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
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MDIO_MMDREG_CTRL2);
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switch (reg & MDIO_PMAPMD_CTRL2_TYPE_MASK) {
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case MDIO_PMAPMD_CTRL2_10G_BT:
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case MDIO_PMAPMD_CTRL2_1G_BT:
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case MDIO_PMAPMD_CTRL2_100_BT:
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case MDIO_PMAPMD_CTRL2_10_BT:
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ecmd->port = PORT_TP;
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ecmd->supported = SUPPORTED_TP;
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reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
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MDIO_MMDREG_SPEED);
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if (reg & (1 << MDIO_MMDREG_SPEED_10G_LBN))
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ecmd->supported |= SUPPORTED_10000baseT_Full;
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if (reg & (1 << MDIO_MMDREG_SPEED_1000M_LBN))
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ecmd->supported |= (SUPPORTED_1000baseT_Full |
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SUPPORTED_1000baseT_Half);
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if (reg & (1 << MDIO_MMDREG_SPEED_100M_LBN))
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ecmd->supported |= (SUPPORTED_100baseT_Full |
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SUPPORTED_100baseT_Half);
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if (reg & (1 << MDIO_MMDREG_SPEED_10M_LBN))
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ecmd->supported |= (SUPPORTED_10baseT_Full |
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SUPPORTED_10baseT_Half);
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ecmd->advertising = ADVERTISED_TP;
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break;
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/* We represent CX4 as fibre in the absence of anything better */
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case MDIO_PMAPMD_CTRL2_10G_CX4:
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/* All the other defined modes are flavours of optical */
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default:
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ecmd->port = PORT_FIBRE;
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ecmd->supported = SUPPORTED_FIBRE;
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ecmd->advertising = ADVERTISED_FIBRE;
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break;
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}
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if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
|
||||
ecmd->supported |= SUPPORTED_Autoneg;
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1);
|
||||
if (reg & BMCR_ANENABLE) {
|
||||
ecmd->autoneg = AUTONEG_ENABLE;
|
||||
ecmd->advertising |=
|
||||
ADVERTISED_Autoneg |
|
||||
mdio_clause45_get_an(efx, MDIO_AN_ADVERTISE) |
|
||||
npage_adv;
|
||||
} else
|
||||
ecmd->autoneg = AUTONEG_DISABLE;
|
||||
} else
|
||||
ecmd->autoneg = AUTONEG_DISABLE;
|
||||
|
||||
if (ecmd->autoneg) {
|
||||
/* If AN is complete, report best common mode,
|
||||
* otherwise report best advertised mode. */
|
||||
u32 modes = 0;
|
||||
if (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_STAT1) &
|
||||
(1 << MDIO_AN_STATUS_AN_DONE_LBN))
|
||||
modes = (ecmd->advertising &
|
||||
(mdio_clause45_get_an(efx, MDIO_AN_LPA) |
|
||||
npage_lpa));
|
||||
if (modes == 0)
|
||||
modes = ecmd->advertising;
|
||||
|
||||
if (modes & ADVERTISED_10000baseT_Full) {
|
||||
ecmd->speed = SPEED_10000;
|
||||
ecmd->duplex = DUPLEX_FULL;
|
||||
} else if (modes & (ADVERTISED_1000baseT_Full |
|
||||
ADVERTISED_1000baseT_Half)) {
|
||||
ecmd->speed = SPEED_1000;
|
||||
ecmd->duplex = !!(modes & ADVERTISED_1000baseT_Full);
|
||||
} else if (modes & (ADVERTISED_100baseT_Full |
|
||||
ADVERTISED_100baseT_Half)) {
|
||||
ecmd->speed = SPEED_100;
|
||||
ecmd->duplex = !!(modes & ADVERTISED_100baseT_Full);
|
||||
} else {
|
||||
ecmd->speed = SPEED_10;
|
||||
ecmd->duplex = !!(modes & ADVERTISED_10baseT_Full);
|
||||
}
|
||||
} else {
|
||||
/* Report forced settings */
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
|
||||
MDIO_MMDREG_CTRL1);
|
||||
ecmd->speed = (((reg & BMCR_SPEED1000) ? 100 : 1) *
|
||||
((reg & BMCR_SPEED100) ? 100 : 10));
|
||||
ecmd->duplex = (reg & BMCR_FULLDPLX ||
|
||||
ecmd->speed == SPEED_10000);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
|
||||
* efx_mdio_set_settings - Set (some of) the PHY settings over MDIO.
|
||||
* @efx: Efx NIC
|
||||
* @ecmd: New settings
|
||||
*/
|
||||
int mdio_clause45_set_settings(struct efx_nic *efx,
|
||||
struct ethtool_cmd *ecmd)
|
||||
int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
int phy_id = efx->mii.phy_id;
|
||||
struct ethtool_cmd prev;
|
||||
u32 required;
|
||||
int reg;
|
||||
@@ -489,94 +305,67 @@ int mdio_clause45_set_settings(struct efx_nic *efx,
|
||||
ADVERTISED_1000baseT_Full))
|
||||
reg |= ADVERTISE_NPAGE;
|
||||
reg |= efx_fc_advertise(efx->wanted_fc);
|
||||
mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_AN_ADVERTISE, reg);
|
||||
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
|
||||
|
||||
/* Set up the (extended) next page if necessary */
|
||||
if (efx->phy_op->set_npage_adv)
|
||||
efx->phy_op->set_npage_adv(efx, ecmd->advertising);
|
||||
|
||||
/* Enable and restart AN */
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1);
|
||||
reg |= BMCR_ANENABLE;
|
||||
reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
|
||||
reg |= MDIO_AN_CTRL1_ENABLE;
|
||||
if (!(EFX_WORKAROUND_15195(efx) &&
|
||||
LOOPBACK_MASK(efx) & efx->phy_op->loopbacks))
|
||||
reg |= BMCR_ANRESTART;
|
||||
reg |= MDIO_AN_CTRL1_RESTART;
|
||||
if (xnp)
|
||||
reg |= 1 << MDIO_AN_CTRL_XNP_LBN;
|
||||
reg |= MDIO_AN_CTRL1_XNP;
|
||||
else
|
||||
reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN);
|
||||
mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1, reg);
|
||||
reg &= ~MDIO_AN_CTRL1_XNP;
|
||||
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
|
||||
} else {
|
||||
/* Disable AN */
|
||||
mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1,
|
||||
__ffs(BMCR_ANENABLE), false);
|
||||
efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_CTRL1,
|
||||
MDIO_AN_CTRL1_ENABLE, false);
|
||||
|
||||
/* Set the basic control bits */
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
|
||||
MDIO_MMDREG_CTRL1);
|
||||
reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX |
|
||||
0x003c);
|
||||
reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1);
|
||||
reg &= ~(MDIO_CTRL1_SPEEDSEL | MDIO_CTRL1_FULLDPLX);
|
||||
if (ecmd->speed == SPEED_100)
|
||||
reg |= BMCR_SPEED100;
|
||||
reg |= MDIO_PMA_CTRL1_SPEED100;
|
||||
if (ecmd->duplex)
|
||||
reg |= BMCR_FULLDPLX;
|
||||
mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
|
||||
MDIO_MMDREG_CTRL1, reg);
|
||||
reg |= MDIO_CTRL1_FULLDPLX;
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mdio_clause45_set_pause(struct efx_nic *efx)
|
||||
void efx_mdio_set_pause(struct efx_nic *efx)
|
||||
{
|
||||
int phy_id = efx->mii.phy_id;
|
||||
int reg;
|
||||
|
||||
if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
|
||||
if (efx->phy_op->mmds & MDIO_DEVS_AN) {
|
||||
/* Set pause capability advertising */
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_AN_ADVERTISE);
|
||||
reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
|
||||
reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
|
||||
reg |= efx_fc_advertise(efx->wanted_fc);
|
||||
mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_AN_ADVERTISE, reg);
|
||||
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
|
||||
|
||||
/* Restart auto-negotiation */
|
||||
reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1);
|
||||
if (reg & BMCR_ANENABLE) {
|
||||
reg |= BMCR_ANRESTART;
|
||||
mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
|
||||
MDIO_MMDREG_CTRL1, reg);
|
||||
reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
|
||||
if (reg & MDIO_AN_CTRL1_ENABLE) {
|
||||
reg |= MDIO_AN_CTRL1_RESTART;
|
||||
efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx)
|
||||
enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx)
|
||||
{
|
||||
int phy_id = efx->mii.phy_id;
|
||||
int lpa;
|
||||
|
||||
if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)))
|
||||
if (!(efx->phy_op->mmds & MDIO_DEVS_AN))
|
||||
return efx->wanted_fc;
|
||||
lpa = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_LPA);
|
||||
lpa = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA);
|
||||
return efx_fc_resolve(efx->wanted_fc, lpa);
|
||||
}
|
||||
|
||||
void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
|
||||
u16 addr, int bit, bool sense)
|
||||
{
|
||||
int old_val = mdio_clause45_read(efx, prt, dev, addr);
|
||||
int new_val;
|
||||
|
||||
if (sense)
|
||||
new_val = old_val | (1 << bit);
|
||||
else
|
||||
new_val = old_val & ~(1 << bit);
|
||||
if (old_val != new_val)
|
||||
mdio_clause45_write(efx, prt, dev, addr, new_val);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user