Merge branch 'next/fixes' of git://git.linaro.org/people/arnd/arm-soc

* 'next/fixes' of git://git.linaro.org/people/arnd/arm-soc: (28 commits)
  ARM: pxa/cm-x300: properly set bt_reset pin
  ARM: mmp: rename SHEEVAD to GPLUGD
  ARM: imx: Fix typo 'MACH_MX31_3DS_MXC_NAND_USE_BBT'
  ARM: i.MX28: shift frac value in _CLK_SET_RATE
  plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired
  ARM: mx5: fix clock usage for suspend
  ARM: pxa: use correct __iomem annotations
  ARM: pxa: sharpsl pm needs SPI
  ARM: pxa: centro and treo680 need palm27x
  ARM: pxa: make pxafb_smart_*() empty when not enabled
  ARM: pxa: select POWER_SUPPLY on raumfeld
  ARM: pxa: pxa95x is incompatible with earlier pxa
  ARM: pxa: CPU_FREQ_TABLE is needed for CPU_FREQ
  ARM: pxa: pxa95x/saarb depends on pxa3xx code
  ARM: pxa: allow selecting just one of TREO680/CENTRO
  ARM: pxa: export symbols from pxa3xx-ulpi
  ARM: pxa: make zylonite_pxa*_init declaration match code
  ARM: pxa/z2: fix building error of pxa27x_cpu_suspend() no longer available
  ARM: at91: add defconfig for at91sam9g45 family
  ARM: at91: remove dependency for Atmel PWM driver selector in Kconfig
  ...

arch/arm/mach-mmp/include/mach/addr-map.h

@@ -11,6 +11,12 @@
 #ifndef __ASM_MACH_ADDR_MAP_H
 #define __ASM_MACH_ADDR_MAP_H
 
+#ifndef __ASSEMBLER__
+#define IOMEM(x)	((void __iomem *)(x))
+#else
+#define IOMEM(x)	(x)
+#endif
+
 /* APB - Application Subsystem Peripheral Bus
  *
  * NOTE: the DMA controller registers are actually on the AXI fabric #1
@@ -18,11 +24,11 @@
  * peripherals on APB, let's count it into the ABP mapping area.
  */
 #define APB_PHYS_BASE		0xd4000000
-#define APB_VIRT_BASE		0xfe000000
+#define APB_VIRT_BASE		IOMEM(0xfe000000)
 #define APB_PHYS_SIZE		0x00200000
 
 #define AXI_PHYS_BASE		0xd4200000
-#define AXI_VIRT_BASE		0xfe200000
+#define AXI_VIRT_BASE		IOMEM(0xfe200000)
 #define AXI_PHYS_SIZE		0x00200000
 
 /* Static Memory Controller - Chip Select 0 and 1 */

arch/arm/mach-mmp/include/mach/gpio-pxa.h

@@ -7,7 +7,7 @@
 #define GPIO_REGS_VIRT	(APB_VIRT_BASE + 0x19000)
 
 #define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)	(*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
+#define GPIO_REG(x)	(GPIO_REGS_VIRT + (x))
 
 #define NR_BUILTIN_GPIO		IRQ_GPIO_NUM