ARM: OMAP1: Move SoC specific headers from plat to mach for omap1
There's no need to have these in plat-omap any longer. Note that these could eventually be made local to mach-omap1 instead of being in mach. But to do that, at least various driver access using omap7xxx.h registers needs to be fixed first. Cc: spi-devel-general@lists.sourceforge.net Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
@@ -311,8 +311,8 @@ static inline u32 omap_cs3_phys(void)
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* ---------------------------------------------------------------------------
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*/
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#include <plat/omap7xx.h>
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#include <plat/omap1510.h>
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#include <plat/omap16xx.h>
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#include "omap7xx.h"
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#include "omap1510.h"
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#include "omap16xx.h"
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#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
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49
arch/arm/mach-omap1/include/mach/omap1510.h
Normal file
49
arch/arm/mach-omap1/include/mach/omap1510.h
Normal file
@@ -0,0 +1,49 @@
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/*
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* Hardware definitions for TI OMAP1510 processor.
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*
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* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_OMAP15XX_H
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#define __ASM_ARCH_OMAP15XX_H
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/*
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* ----------------------------------------------------------------------------
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* Base addresses
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* ----------------------------------------------------------------------------
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*/
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/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
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#define OMAP1510_DSP_BASE 0xE0000000
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#define OMAP1510_DSP_SIZE 0x28000
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#define OMAP1510_DSP_START 0xE0000000
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#define OMAP1510_DSPREG_BASE 0xE1000000
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#define OMAP1510_DSPREG_SIZE SZ_128K
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#define OMAP1510_DSPREG_START 0xE1000000
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#define OMAP1510_DSP_MMU_BASE (0xfffed200)
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#endif /* __ASM_ARCH_OMAP15XX_H */
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201
arch/arm/mach-omap1/include/mach/omap16xx.h
Normal file
201
arch/arm/mach-omap1/include/mach/omap16xx.h
Normal file
@@ -0,0 +1,201 @@
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/*
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* Hardware definitions for TI OMAP1610/5912/1710 processors.
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*
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* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_OMAP16XX_H
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#define __ASM_ARCH_OMAP16XX_H
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/*
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* ----------------------------------------------------------------------------
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* Base addresses
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* ----------------------------------------------------------------------------
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*/
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/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
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#define OMAP16XX_DSP_BASE 0xE0000000
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#define OMAP16XX_DSP_SIZE 0x28000
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#define OMAP16XX_DSP_START 0xE0000000
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#define OMAP16XX_DSPREG_BASE 0xE1000000
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#define OMAP16XX_DSPREG_SIZE SZ_128K
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#define OMAP16XX_DSPREG_START 0xE1000000
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#define OMAP16XX_SEC_BASE 0xFFFE4000
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#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
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#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
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#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
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/*
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* ---------------------------------------------------------------------------
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* Interrupts
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* ---------------------------------------------------------------------------
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*/
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#define OMAP_IH2_0_BASE (0xfffe0000)
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#define OMAP_IH2_1_BASE (0xfffe0100)
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#define OMAP_IH2_2_BASE (0xfffe0200)
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#define OMAP_IH2_3_BASE (0xfffe0300)
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#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
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#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
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#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
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#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
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#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
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#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
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#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
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#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
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#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
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#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
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#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
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#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
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#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
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#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
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#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
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#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
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#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
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#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
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#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
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#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
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#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
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#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
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#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
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#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
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#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
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#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
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#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
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#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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* ----------------------------------------------------------------------------
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*/
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#define OMAP16XX_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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/*
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* ----------------------------------------------------------------------------
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* Pin configuration registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV6 (1 << 8)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV7 (1 << 9)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV8 (1 << 10)
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#define OMAP16XX_CONF_VOLTAGE_VDDSHV9 (1 << 11)
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#define OMAP16XX_SUBLVDS_CONF_VALID (1 << 13)
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/*
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* ----------------------------------------------------------------------------
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* System control registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP1610_RESET_CONTROL 0xfffe1140
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/*
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* ---------------------------------------------------------------------------
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* TIPB bus interface
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* ---------------------------------------------------------------------------
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*/
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#define TIPB_SWITCH_BASE (0xfffbc800)
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#define OMAP16XX_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_BASE + 0x160)
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/* UART3 Registers Mapping through MPU bus */
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#define UART3_RHR (OMAP1_UART3_BASE + 0)
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#define UART3_THR (OMAP1_UART3_BASE + 0)
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#define UART3_DLL (OMAP1_UART3_BASE + 0)
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#define UART3_IER (OMAP1_UART3_BASE + 4)
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#define UART3_DLH (OMAP1_UART3_BASE + 4)
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#define UART3_IIR (OMAP1_UART3_BASE + 8)
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#define UART3_FCR (OMAP1_UART3_BASE + 8)
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#define UART3_EFR (OMAP1_UART3_BASE + 8)
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#define UART3_LCR (OMAP1_UART3_BASE + 0x0C)
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#define UART3_MCR (OMAP1_UART3_BASE + 0x10)
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#define UART3_XON1_ADDR1 (OMAP1_UART3_BASE + 0x10)
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#define UART3_XON2_ADDR2 (OMAP1_UART3_BASE + 0x14)
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#define UART3_LSR (OMAP1_UART3_BASE + 0x14)
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#define UART3_TCR (OMAP1_UART3_BASE + 0x18)
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#define UART3_MSR (OMAP1_UART3_BASE + 0x18)
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#define UART3_XOFF1 (OMAP1_UART3_BASE + 0x18)
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#define UART3_XOFF2 (OMAP1_UART3_BASE + 0x1C)
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#define UART3_SPR (OMAP1_UART3_BASE + 0x1C)
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#define UART3_TLR (OMAP1_UART3_BASE + 0x1C)
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#define UART3_MDR1 (OMAP1_UART3_BASE + 0x20)
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#define UART3_MDR2 (OMAP1_UART3_BASE + 0x24)
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#define UART3_SFLSR (OMAP1_UART3_BASE + 0x28)
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#define UART3_TXFLL (OMAP1_UART3_BASE + 0x28)
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#define UART3_RESUME (OMAP1_UART3_BASE + 0x2C)
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#define UART3_TXFLH (OMAP1_UART3_BASE + 0x2C)
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#define UART3_SFREGL (OMAP1_UART3_BASE + 0x30)
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#define UART3_RXFLL (OMAP1_UART3_BASE + 0x30)
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#define UART3_SFREGH (OMAP1_UART3_BASE + 0x34)
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#define UART3_RXFLH (OMAP1_UART3_BASE + 0x34)
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#define UART3_BLR (OMAP1_UART3_BASE + 0x38)
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#define UART3_ACREG (OMAP1_UART3_BASE + 0x3C)
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#define UART3_DIV16 (OMAP1_UART3_BASE + 0x3C)
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#define UART3_SCR (OMAP1_UART3_BASE + 0x40)
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#define UART3_SSR (OMAP1_UART3_BASE + 0x44)
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#define UART3_EBLR (OMAP1_UART3_BASE + 0x48)
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#define UART3_OSC_12M_SEL (OMAP1_UART3_BASE + 0x4C)
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#define UART3_MVR (OMAP1_UART3_BASE + 0x50)
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/*
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* ---------------------------------------------------------------------------
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* Watchdog timer
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* ---------------------------------------------------------------------------
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*/
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/* 32-bit Watchdog timer in OMAP 16XX */
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#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
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#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
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#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
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#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
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#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
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#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
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#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
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#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
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#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
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#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
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#define WCLR_PRE_SHIFT 5
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#define WCLR_PTV_SHIFT 2
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#define WWPS_W_PEND_WSPR (1 << 4)
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#define WWPS_W_PEND_WTGR (1 << 3)
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#define WWPS_W_PEND_WLDR (1 << 2)
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#define WWPS_W_PEND_WCRR (1 << 1)
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#define WWPS_W_PEND_WCLR (1 << 0)
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#define WSPR_ENABLE_0 (0x0000bbbb)
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#define WSPR_ENABLE_1 (0x00004444)
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#define WSPR_DISABLE_0 (0x0000aaaa)
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#define WSPR_DISABLE_1 (0x00005555)
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#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
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#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
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#endif /* __ASM_ARCH_OMAP16XX_H */
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106
arch/arm/mach-omap1/include/mach/omap7xx.h
Normal file
106
arch/arm/mach-omap1/include/mach/omap7xx.h
Normal file
@@ -0,0 +1,106 @@
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/*
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* Hardware definitions for TI OMAP7XX processor.
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*
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* Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
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* Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
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* Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
|
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* under the terms of the GNU General Public License as published by the
|
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* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
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|
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#ifndef __ASM_ARCH_OMAP7XX_H
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#define __ASM_ARCH_OMAP7XX_H
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/*
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* ----------------------------------------------------------------------------
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* Base addresses
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* ----------------------------------------------------------------------------
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*/
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/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
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#define OMAP7XX_DSP_BASE 0xE0000000
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#define OMAP7XX_DSP_SIZE 0x50000
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#define OMAP7XX_DSP_START 0xE0000000
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#define OMAP7XX_DSPREG_BASE 0xE1000000
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#define OMAP7XX_DSPREG_SIZE SZ_128K
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#define OMAP7XX_DSPREG_START 0xE1000000
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#define OMAP7XX_SPI1_BASE 0xfffc0800
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#define OMAP7XX_SPI2_BASE 0xfffc1000
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/*
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* ----------------------------------------------------------------------------
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* OMAP7XX specific configuration registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP7XX_CONFIG_BASE 0xfffe1000
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#define OMAP7XX_IO_CONF_0 0xfffe1070
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#define OMAP7XX_IO_CONF_1 0xfffe1074
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#define OMAP7XX_IO_CONF_2 0xfffe1078
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#define OMAP7XX_IO_CONF_3 0xfffe107c
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#define OMAP7XX_IO_CONF_4 0xfffe1080
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#define OMAP7XX_IO_CONF_5 0xfffe1084
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#define OMAP7XX_IO_CONF_6 0xfffe1088
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#define OMAP7XX_IO_CONF_7 0xfffe108c
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#define OMAP7XX_IO_CONF_8 0xfffe1090
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#define OMAP7XX_IO_CONF_9 0xfffe1094
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#define OMAP7XX_IO_CONF_10 0xfffe1098
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#define OMAP7XX_IO_CONF_11 0xfffe109c
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#define OMAP7XX_IO_CONF_12 0xfffe10a0
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#define OMAP7XX_IO_CONF_13 0xfffe10a4
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#define OMAP7XX_MODE_1 0xfffe1010
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#define OMAP7XX_MODE_2 0xfffe1014
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/* CSMI specials: in terms of base + offset */
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#define OMAP7XX_MODE2_OFFSET 0x14
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/*
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* ----------------------------------------------------------------------------
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* OMAP7XX traffic controller configuration registers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP7XX_FLASH_CFG_0 0xfffecc10
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#define OMAP7XX_FLASH_ACFG_0 0xfffecc50
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#define OMAP7XX_FLASH_CFG_1 0xfffecc14
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#define OMAP7XX_FLASH_ACFG_1 0xfffecc54
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/*
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* ----------------------------------------------------------------------------
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||||
* OMAP7XX DSP control registers
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||||
* ----------------------------------------------------------------------------
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||||
*/
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#define OMAP7XX_ICR_BASE 0xfffbb800
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#define OMAP7XX_DSP_M_CTL 0xfffbb804
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#define OMAP7XX_DSP_MMU_BASE 0xfffed200
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||||
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||||
/*
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||||
* ----------------------------------------------------------------------------
|
||||
* OMAP7XX PCC_UPLD configuration registers
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP7XX_PCC_UPLD_CTRL_BASE (0xfffe0900)
|
||||
#define OMAP7XX_PCC_UPLD_CTRL (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP7XX_H */
|
||||
|
||||
Reference in New Issue
Block a user