MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.
While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -62,7 +62,6 @@ obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
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obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
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obj-$(CONFIG_I8259) += i8259.o
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obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
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obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
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obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
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obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
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@@ -1,169 +0,0 @@
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/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
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* Author: Maciej W. Rozycki <macro@mips.com>
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*
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* This file define the irq handler for MIPS CPU interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Almost all MIPS CPUs define 8 interrupt sources. They are typically
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* level triggered (i.e., cannot be cleared from CPU; must be cleared from
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* device). The first two are software interrupts which we don't really
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* use or support. The last one is usually the CPU timer interrupt if
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* counter register is present or, for CPUs with an external FPU, by
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* convention it's the FPU exception interrupt.
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*
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* Don't even think about using this on SMP. You have been warned.
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*
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* This file exports one global function:
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* void mips_cpu_irq_init(void);
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/setup.h>
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static inline void unmask_mips_irq(struct irq_data *d)
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{
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set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_enable_hazard();
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}
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static inline void mask_mips_irq(struct irq_data *d)
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{
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clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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irq_disable_hazard();
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}
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static struct irq_chip mips_cpu_irq_controller = {
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.name = "MIPS",
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.irq_ack = mask_mips_irq,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mask_mips_irq,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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};
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/*
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* Basically the same as above but taking care of all the MT stuff
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*/
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static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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unmask_mips_irq(d);
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return 0;
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for mips_cpu_irq_end.
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*/
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static void mips_mt_cpu_irq_ack(struct irq_data *d)
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{
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unsigned int vpflags = dvpe();
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clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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evpe(vpflags);
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mask_mips_irq(d);
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}
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static struct irq_chip mips_mt_cpu_irq_controller = {
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.name = "MIPS",
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.irq_startup = mips_mt_cpu_irq_startup,
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.irq_ack = mips_mt_cpu_irq_ack,
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.irq_mask = mask_mips_irq,
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.irq_mask_ack = mips_mt_cpu_irq_ack,
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.irq_unmask = unmask_mips_irq,
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.irq_eoi = unmask_mips_irq,
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.irq_disable = mask_mips_irq,
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.irq_enable = unmask_mips_irq,
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};
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asmlinkage void __weak plat_irq_dispatch(void)
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{
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unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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pending &= ~BIT(irq);
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}
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}
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static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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static struct irq_chip *chip;
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if (hw < 2 && cpu_has_mipsmt) {
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/* Software interrupts are used for MT/CMT IPI */
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chip = &mips_mt_cpu_irq_controller;
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} else {
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chip = &mips_cpu_irq_controller;
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}
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if (cpu_has_vint)
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set_vi_handler(hw, plat_irq_dispatch);
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irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
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return 0;
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}
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static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
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.map = mips_cpu_intc_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void __init __mips_cpu_irq_init(struct device_node *of_node)
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{
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struct irq_domain *domain;
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/* Mask interrupts. */
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clear_c0_status(ST0_IM);
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clear_c0_cause(CAUSEF_IP);
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domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
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&mips_cpu_intc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add irqdomain for MIPS CPU");
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}
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void __init mips_cpu_irq_init(void)
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{
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__mips_cpu_irq_init(NULL);
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}
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int __init mips_cpu_irq_of_init(struct device_node *of_node,
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struct device_node *parent)
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{
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__mips_cpu_irq_init(of_node);
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return 0;
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}
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