Merge branch 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2016-05-22: - cmd-parser support for direct reg->reg loads (Ken Graunke) - better handle DP++ smart dongles (Ville) - bxt guc fw loading support (Nick Hoathe) - remove a bunch of struct typedefs from dpll code (Ander) - tons of small work all over to avoid casting between drm_device and the i915 dev struct (Tvrtko&Chris) - untangle request retiring from other operations, also fixes reset stat corner cases (Chris) - skl atomic watermark support from Matt Roper, yay! - various wm handling bugfixes from Ville - big pile of cdclck rework for bxt/skl (Ville) - CABC (Content Adaptive Brigthness Control) for dsi panels (Jani&Deepak M) - nonblocking atomic commits for plane-only updates (Maarten Lankhorst) - bunch of PSR fixes&improvements - untangle our map/pin/sg_iter code a bit (Dave Gordon) drm-intel-next-2016-05-08: - refactor stolen quirks to share code between early quirks and i915 (Joonas) - refactor gem BO/vma funcstion (Tvrtko&Dave) - backlight over DPCD support (Yetunde Abedisi) - more dsi panel sequence support (Jani) - lots of refactoring around handling iomaps, vma, ring access and related topics culmulating in removing the duplicated request tracking in the execlist code (Chris & Tvrtko) includes a small patch for core iomapping code - hw state readout for bxt dsi (Ramalingam C) - cdclk cleanups (Ville) - dedupe chv pll code a bit (Ander) - enable semaphores on gen8+ for legacy submission, to be able to have a direct comparison against execlist on the same platform (Chris) Not meant to be used for anything else but performance tuning - lvds border bit hw state checker fix (Jani) - rpm vs. shrinker/oom-notifier fixes (Praveen Paneri) - l3 tuning (Imre) - revert mst dp audio, it's totally non-functional and crash-y (Lyude) - first official dmc for kbl (Rodrigo) - and tons of small things all over as usual * 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel: (194 commits) drm/i915: Revert async unpin and nonblocking atomic commit drm/i915: Update DRIVER_DATE to 20160522 drm/i915: Inline sg_next() for the optimised SGL iterator drm/i915: Introduce & use new lightweight SGL iterators drm/i915: optimise i915_gem_object_map() for small objects drm/i915: refactor i915_gem_object_pin_map() drm/i915/psr: Implement PSR2 w/a for gen9 drm/i915/psr: Use ->get_aux_send_ctl functions drm/i915/psr: Order DP aux transactions correctly drm/i915/psr: Make idle_frames sensible again drm/i915/psr: Try to program link training times correctly drm/i915/userptr: Convert to drm_i915_private drm/i915: Allow nonblocking update of pageflips. drm/i915: Check for unpin correctness. Reapply "drm/i915: Avoid stalling on pending flips for legacy cursor updates" drm/i915: Make unpin async. drm/i915: Prepare connectors for nonblocking checks. drm/i915: Pass atomic states to fbc update functions. drm/i915: Remove reset_counter from intel_crtc. drm/i915: Remove queue_flip pointer. ...
This commit is contained in:
Dave Airlie
@@ -223,36 +223,19 @@ static void __init intel_remapping_check(int num, int slot, int func)
|
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* despite the efforts of the "RAM buffer" approach, which simply rounds
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* memory boundaries up to 64M to try to catch space that may decode
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* as RAM and so is not suitable for MMIO.
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*
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* And yes, so far on current devices the base addr is always under 4G.
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*/
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static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
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{
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u32 base;
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/*
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* For the PCI IDs in this quirk, the stolen base is always
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* in 0x5c, aka the BDSM register (yes that's really what
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* it's called).
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*/
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base = read_pci_config(num, slot, func, 0x5c);
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base &= ~((1<<20) - 1);
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return base;
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}
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#define KB(x) ((x) * 1024UL)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init i830_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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if (tmp & I830_TSEG_SIZE_1M)
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if (esmramc & I830_TSEG_SIZE_1M)
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return MB(1);
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else
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return KB(512);
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@@ -260,27 +243,26 @@ static size_t __init i830_tseg_size(void)
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static size_t __init i845_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
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if (!(tmp & TSEG_ENABLE))
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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switch (tmp & I845_TSEG_SIZE_MASK) {
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case I845_TSEG_SIZE_512K:
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return KB(512);
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case I845_TSEG_SIZE_1M:
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return MB(1);
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switch (tseg_size) {
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case I845_TSEG_SIZE_512K: return KB(512);
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case I845_TSEG_SIZE_1M: return MB(1);
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default:
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WARN_ON(1);
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return 0;
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WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
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}
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return 0;
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}
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static size_t __init i85x_tseg_size(void)
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{
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u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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if (!(tmp & TSEG_ENABLE))
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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return MB(1);
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@@ -300,285 +282,287 @@ static size_t __init i85x_mem_size(void)
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* On 830/845/85x the stolen memory base isn't available in any
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* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
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*/
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static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
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static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
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size_t stolen_size)
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{
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return i830_mem_size() - i830_tseg_size() - stolen_size;
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return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
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}
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static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
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static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
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size_t stolen_size)
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{
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return i830_mem_size() - i845_tseg_size() - stolen_size;
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return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
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}
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static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
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static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
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size_t stolen_size)
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{
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return i85x_mem_size() - i85x_tseg_size() - stolen_size;
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return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
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}
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static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
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static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
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size_t stolen_size)
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{
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u16 toud;
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/*
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* FIXME is the graphics stolen memory region
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* always at TOUD? Ie. is it always the last
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* one to be allocated by the BIOS?
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*/
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return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
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toud = read_pci_config_16(0, 0, 0, I865_TOUD);
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return (phys_addr_t)toud << 16;
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}
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static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
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size_t stolen_size)
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{
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u32 bsm;
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/* Almost universally we can find the Graphics Base of Stolen Memory
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* at register BSM (0x5c) in the igfx configuration space. On a few
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* (desktop) machines this is also mirrored in the bridge device at
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* different locations, or in the MCHBAR.
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*/
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bsm = read_pci_config(num, slot, func, INTEL_BSM);
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return (phys_addr_t)bsm & INTEL_BSM_MASK;
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}
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static size_t __init i830_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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gms = gmch_ctrl & I830_GMCH_GMS_MASK;
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switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
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case I830_GMCH_GMS_STOLEN_512:
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stolen_size = KB(512);
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break;
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case I830_GMCH_GMS_STOLEN_1024:
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stolen_size = MB(1);
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break;
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case I830_GMCH_GMS_STOLEN_8192:
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stolen_size = MB(8);
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break;
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case I830_GMCH_GMS_LOCAL:
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/* local memory isn't part of the normal address space */
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stolen_size = 0;
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break;
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switch (gms) {
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case I830_GMCH_GMS_STOLEN_512: return KB(512);
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case I830_GMCH_GMS_STOLEN_1024: return MB(1);
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case I830_GMCH_GMS_STOLEN_8192: return MB(8);
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/* local memory isn't part of the normal address space */
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case I830_GMCH_GMS_LOCAL: return 0;
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default:
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return 0;
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WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
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}
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return stolen_size;
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return 0;
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}
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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gms = gmch_ctrl & I855_GMCH_GMS_MASK;
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switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
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case I855_GMCH_GMS_STOLEN_1M:
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stolen_size = MB(1);
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break;
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case I855_GMCH_GMS_STOLEN_4M:
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stolen_size = MB(4);
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break;
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case I855_GMCH_GMS_STOLEN_8M:
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stolen_size = MB(8);
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break;
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case I855_GMCH_GMS_STOLEN_16M:
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stolen_size = MB(16);
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break;
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case I855_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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stolen_size = MB(48);
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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switch (gms) {
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case I855_GMCH_GMS_STOLEN_1M: return MB(1);
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case I855_GMCH_GMS_STOLEN_4M: return MB(4);
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case I855_GMCH_GMS_STOLEN_8M: return MB(8);
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case I855_GMCH_GMS_STOLEN_16M: return MB(16);
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case I855_GMCH_GMS_STOLEN_32M: return MB(32);
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case I915_GMCH_GMS_STOLEN_48M: return MB(48);
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case I915_GMCH_GMS_STOLEN_64M: return MB(64);
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case G33_GMCH_GMS_STOLEN_128M: return MB(128);
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case G33_GMCH_GMS_STOLEN_256M: return MB(256);
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case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
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case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
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case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
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case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
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default:
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stolen_size = 0;
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break;
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WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
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}
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return stolen_size;
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return 0;
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}
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static size_t __init gen6_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
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gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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return (size_t)gms * MB(32);
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}
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static size_t __init gen8_stolen_size(int num, int slot, int func)
|
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
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gmch_ctrl &= BDW_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
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return (size_t)gms * MB(32);
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}
|
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|
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static size_t __init chv_stolen_size(int num, int slot, int func)
|
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{
|
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u16 gmch_ctrl;
|
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u16 gms;
|
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|
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
|
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
|
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
|
||||
gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
|
||||
|
||||
/*
|
||||
* 0x0 to 0x10: 32MB increments starting at 0MB
|
||||
* 0x11 to 0x16: 4MB increments starting at 8MB
|
||||
* 0x17 to 0x1d: 4MB increments start at 36MB
|
||||
*/
|
||||
if (gmch_ctrl < 0x11)
|
||||
return gmch_ctrl << 25;
|
||||
else if (gmch_ctrl < 0x17)
|
||||
return (gmch_ctrl - 0x11 + 2) << 22;
|
||||
if (gms < 0x11)
|
||||
return (size_t)gms * MB(32);
|
||||
else if (gms < 0x17)
|
||||
return (size_t)(gms - 0x11 + 2) * MB(4);
|
||||
else
|
||||
return (gmch_ctrl - 0x17 + 9) << 22;
|
||||
return (size_t)(gms - 0x17 + 9) * MB(4);
|
||||
}
|
||||
|
||||
struct intel_stolen_funcs {
|
||||
size_t (*size)(int num, int slot, int func);
|
||||
u32 (*base)(int num, int slot, int func, size_t size);
|
||||
};
|
||||
|
||||
static size_t __init gen9_stolen_size(int num, int slot, int func)
|
||||
{
|
||||
u16 gmch_ctrl;
|
||||
u16 gms;
|
||||
|
||||
gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
|
||||
gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
|
||||
gmch_ctrl &= BDW_GMCH_GMS_MASK;
|
||||
gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
|
||||
|
||||
if (gmch_ctrl < 0xf0)
|
||||
return gmch_ctrl << 25; /* 32 MB units */
|
||||
/* 0x0 to 0xef: 32MB increments starting at 0MB */
|
||||
/* 0xf0 to 0xfe: 4MB increments starting at 4MB */
|
||||
if (gms < 0xf0)
|
||||
return (size_t)gms * MB(32);
|
||||
else
|
||||
/* 4MB increments starting at 0xf0 for 4MB */
|
||||
return (gmch_ctrl - 0xf0 + 1) << 22;
|
||||
return (size_t)(gms - 0xf0 + 1) * MB(4);
|
||||
}
|
||||
|
||||
typedef size_t (*stolen_size_fn)(int num, int slot, int func);
|
||||
|
||||
static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
|
||||
.base = i830_stolen_base,
|
||||
.size = i830_stolen_size,
|
||||
struct intel_early_ops {
|
||||
size_t (*stolen_size)(int num, int slot, int func);
|
||||
phys_addr_t (*stolen_base)(int num, int slot, int func, size_t size);
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
|
||||
.base = i845_stolen_base,
|
||||
.size = i830_stolen_size,
|
||||
static const struct intel_early_ops i830_early_ops __initconst = {
|
||||
.stolen_base = i830_stolen_base,
|
||||
.stolen_size = i830_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
|
||||
.base = i85x_stolen_base,
|
||||
.size = gen3_stolen_size,
|
||||
static const struct intel_early_ops i845_early_ops __initconst = {
|
||||
.stolen_base = i845_stolen_base,
|
||||
.stolen_size = i830_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
|
||||
.base = i865_stolen_base,
|
||||
.size = gen3_stolen_size,
|
||||
static const struct intel_early_ops i85x_early_ops __initconst = {
|
||||
.stolen_base = i85x_stolen_base,
|
||||
.stolen_size = gen3_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
|
||||
.base = intel_stolen_base,
|
||||
.size = gen3_stolen_size,
|
||||
static const struct intel_early_ops i865_early_ops __initconst = {
|
||||
.stolen_base = i865_stolen_base,
|
||||
.stolen_size = gen3_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
|
||||
.base = intel_stolen_base,
|
||||
.size = gen6_stolen_size,
|
||||
static const struct intel_early_ops gen3_early_ops __initconst = {
|
||||
.stolen_base = gen3_stolen_base,
|
||||
.stolen_size = gen3_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
|
||||
.base = intel_stolen_base,
|
||||
.size = gen8_stolen_size,
|
||||
static const struct intel_early_ops gen6_early_ops __initconst = {
|
||||
.stolen_base = gen3_stolen_base,
|
||||
.stolen_size = gen6_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs gen9_stolen_funcs __initconst = {
|
||||
.base = intel_stolen_base,
|
||||
.size = gen9_stolen_size,
|
||||
static const struct intel_early_ops gen8_early_ops __initconst = {
|
||||
.stolen_base = gen3_stolen_base,
|
||||
.stolen_size = gen8_stolen_size,
|
||||
};
|
||||
|
||||
static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
|
||||
.base = intel_stolen_base,
|
||||
.size = chv_stolen_size,
|
||||
static const struct intel_early_ops gen9_early_ops __initconst = {
|
||||
.stolen_base = gen3_stolen_base,
|
||||
.stolen_size = gen9_stolen_size,
|
||||
};
|
||||
|
||||
static const struct pci_device_id intel_stolen_ids[] __initconst = {
|
||||
INTEL_I830_IDS(&i830_stolen_funcs),
|
||||
INTEL_I845G_IDS(&i845_stolen_funcs),
|
||||
INTEL_I85X_IDS(&i85x_stolen_funcs),
|
||||
INTEL_I865G_IDS(&i865_stolen_funcs),
|
||||
INTEL_I915G_IDS(&gen3_stolen_funcs),
|
||||
INTEL_I915GM_IDS(&gen3_stolen_funcs),
|
||||
INTEL_I945G_IDS(&gen3_stolen_funcs),
|
||||
INTEL_I945GM_IDS(&gen3_stolen_funcs),
|
||||
INTEL_VLV_M_IDS(&gen6_stolen_funcs),
|
||||
INTEL_VLV_D_IDS(&gen6_stolen_funcs),
|
||||
INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
|
||||
INTEL_I965G_IDS(&gen3_stolen_funcs),
|
||||
INTEL_G33_IDS(&gen3_stolen_funcs),
|
||||
INTEL_I965GM_IDS(&gen3_stolen_funcs),
|
||||
INTEL_GM45_IDS(&gen3_stolen_funcs),
|
||||
INTEL_G45_IDS(&gen3_stolen_funcs),
|
||||
INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
|
||||
INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
|
||||
INTEL_SNB_D_IDS(&gen6_stolen_funcs),
|
||||
INTEL_SNB_M_IDS(&gen6_stolen_funcs),
|
||||
INTEL_IVB_M_IDS(&gen6_stolen_funcs),
|
||||
INTEL_IVB_D_IDS(&gen6_stolen_funcs),
|
||||
INTEL_HSW_D_IDS(&gen6_stolen_funcs),
|
||||
INTEL_HSW_M_IDS(&gen6_stolen_funcs),
|
||||
INTEL_BDW_M_IDS(&gen8_stolen_funcs),
|
||||
INTEL_BDW_D_IDS(&gen8_stolen_funcs),
|
||||
INTEL_CHV_IDS(&chv_stolen_funcs),
|
||||
INTEL_SKL_IDS(&gen9_stolen_funcs),
|
||||
INTEL_BXT_IDS(&gen9_stolen_funcs),
|
||||
INTEL_KBL_IDS(&gen9_stolen_funcs),
|
||||
static const struct intel_early_ops chv_early_ops __initconst = {
|
||||
.stolen_base = gen3_stolen_base,
|
||||
.stolen_size = chv_stolen_size,
|
||||
};
|
||||
|
||||
static void __init intel_graphics_stolen(int num, int slot, int func)
|
||||
static const struct pci_device_id intel_early_ids[] __initconst = {
|
||||
INTEL_I830_IDS(&i830_early_ops),
|
||||
INTEL_I845G_IDS(&i845_early_ops),
|
||||
INTEL_I85X_IDS(&i85x_early_ops),
|
||||
INTEL_I865G_IDS(&i865_early_ops),
|
||||
INTEL_I915G_IDS(&gen3_early_ops),
|
||||
INTEL_I915GM_IDS(&gen3_early_ops),
|
||||
INTEL_I945G_IDS(&gen3_early_ops),
|
||||
INTEL_I945GM_IDS(&gen3_early_ops),
|
||||
INTEL_VLV_M_IDS(&gen6_early_ops),
|
||||
INTEL_VLV_D_IDS(&gen6_early_ops),
|
||||
INTEL_PINEVIEW_IDS(&gen3_early_ops),
|
||||
INTEL_I965G_IDS(&gen3_early_ops),
|
||||
INTEL_G33_IDS(&gen3_early_ops),
|
||||
INTEL_I965GM_IDS(&gen3_early_ops),
|
||||
INTEL_GM45_IDS(&gen3_early_ops),
|
||||
INTEL_G45_IDS(&gen3_early_ops),
|
||||
INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
|
||||
INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
|
||||
INTEL_SNB_D_IDS(&gen6_early_ops),
|
||||
INTEL_SNB_M_IDS(&gen6_early_ops),
|
||||
INTEL_IVB_M_IDS(&gen6_early_ops),
|
||||
INTEL_IVB_D_IDS(&gen6_early_ops),
|
||||
INTEL_HSW_D_IDS(&gen6_early_ops),
|
||||
INTEL_HSW_M_IDS(&gen6_early_ops),
|
||||
INTEL_BDW_M_IDS(&gen8_early_ops),
|
||||
INTEL_BDW_D_IDS(&gen8_early_ops),
|
||||
INTEL_CHV_IDS(&chv_early_ops),
|
||||
INTEL_SKL_IDS(&gen9_early_ops),
|
||||
INTEL_BXT_IDS(&gen9_early_ops),
|
||||
INTEL_KBL_IDS(&gen9_early_ops),
|
||||
};
|
||||
|
||||
static void __init
|
||||
intel_graphics_stolen(int num, int slot, int func,
|
||||
const struct intel_early_ops *early_ops)
|
||||
{
|
||||
phys_addr_t base, end;
|
||||
size_t size;
|
||||
|
||||
size = early_ops->stolen_size(num, slot, func);
|
||||
base = early_ops->stolen_base(num, slot, func, size);
|
||||
|
||||
if (!size || !base)
|
||||
return;
|
||||
|
||||
end = base + size - 1;
|
||||
printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n",
|
||||
&base, &end);
|
||||
|
||||
/* Mark this space as reserved */
|
||||
e820_add_region(base, size, E820_RESERVED);
|
||||
sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
|
||||
}
|
||||
|
||||
static void __init intel_graphics_quirks(int num, int slot, int func)
|
||||
{
|
||||
const struct intel_early_ops *early_ops;
|
||||
u16 device;
|
||||
int i;
|
||||
u32 start;
|
||||
u16 device, subvendor, subdevice;
|
||||
|
||||
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
||||
subvendor = read_pci_config_16(num, slot, func,
|
||||
PCI_SUBSYSTEM_VENDOR_ID);
|
||||
subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
|
||||
if (intel_stolen_ids[i].device == device) {
|
||||
const struct intel_stolen_funcs *stolen_funcs =
|
||||
(const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
|
||||
size = stolen_funcs->size(num, slot, func);
|
||||
start = stolen_funcs->base(num, slot, func, size);
|
||||
if (size && start) {
|
||||
printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
|
||||
start, start + (u32)size - 1);
|
||||
/* Mark this space as reserved */
|
||||
e820_add_region(start, size, E820_RESERVED);
|
||||
sanitize_e820_map(e820.map,
|
||||
ARRAY_SIZE(e820.map),
|
||||
&e820.nr_map);
|
||||
}
|
||||
return;
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
|
||||
kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
|
||||
|
||||
if (intel_early_ids[i].device != device)
|
||||
continue;
|
||||
|
||||
early_ops = (typeof(early_ops))driver_data;
|
||||
|
||||
intel_graphics_stolen(num, slot, func, early_ops);
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -627,7 +611,7 @@ static struct chipset early_qrk[] __initdata = {
|
||||
{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
|
||||
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
|
||||
QFLAG_APPLY_ONCE, intel_graphics_stolen },
|
||||
QFLAG_APPLY_ONCE, intel_graphics_quirks },
|
||||
/*
|
||||
* HPET on the current version of the Baytrail platform has accuracy
|
||||
* problems: it will halt in deep idle state - so we disable it.
|
||||
|
||||
Reference in New Issue
Block a user