sh: Convert INTC2 to IRQ table registration.
Currently the INTC2 code contains a fixed IRQ table that it iterates through to set the handler type, we move this in to the CPU subtype setup code instead and allow for submitting the table that way. This drops the ST40 tables, as nothing has been happening with those processors, while converting the only existing users to use the new table directly (SH7760 and SH7780). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
@@ -11,10 +11,9 @@
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* Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <asm/io.h>
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static void disable_intc2_irq(unsigned int irq)
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{
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@@ -45,151 +44,36 @@ static struct irq_chip intc2_irq_chip = {
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* PIO1 which is INTPRI00[19,16] and INTMSK00[13]
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* would be: ^ ^ ^ ^
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* | | | |
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* make_intc2_irq(84, 0, 16, 0, 13);
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* { 84, 0, 16, 0, 13 },
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*
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* in the intc2_data table.
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*/
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void make_intc2_irq(struct intc2_data *p)
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{
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unsigned int flags;
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unsigned long ipr;
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disable_irq_nosync(p->irq);
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
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local_irq_restore(flags);
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set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data(p->irq, p);
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enable_intc2_irq(p->irq);
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}
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static struct intc2_data intc2_irq_table[] = {
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#if defined(CONFIG_CPU_SUBTYPE_ST40)
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{64, 0, 0, 0, 0, 13}, /* PCI serr */
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{65, 0, 4, 0, 1, 13}, /* PCI err */
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{66, 0, 4, 0, 2, 13}, /* PCI ad */
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{67, 0, 4, 0, 3, 13}, /* PCI pwd down */
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{72, 0, 8, 0, 5, 13}, /* DMAC INT0 */
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{73, 0, 8, 0, 6, 13}, /* DMAC INT1 */
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{74, 0, 8, 0, 7, 13}, /* DMAC INT2 */
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{75, 0, 8, 0, 8, 13}, /* DMAC INT3 */
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{76, 0, 8, 0, 9, 13}, /* DMAC INT4 */
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{78, 0, 8, 0, 11, 13}, /* DMAC ERR */
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{80, 0, 12, 0, 12, 13}, /* PIO0 */
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{84, 0, 16, 0, 13, 13}, /* PIO1 */
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{88, 0, 20, 0, 14, 13}, /* PIO2 */
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{112, 4, 0, 4, 0, 13}, /* Mailbox */
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#ifdef CONFIG_CPU_SUBTYPE_ST40GX1
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{116, 4, 4, 4, 4, 13}, /* SSC0 */
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{120, 4, 8, 4, 8, 13}, /* IR Blaster */
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{124, 4, 12, 4, 12, 13}, /* USB host */
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{128, 4, 16, 4, 16, 13}, /* Video processor BLITTER */
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{132, 4, 20, 4, 20, 13}, /* UART0 */
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{134, 4, 20, 4, 22, 13}, /* UART2 */
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{136, 4, 24, 4, 24, 13}, /* IO_PIO0 */
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{140, 4, 28, 4, 28, 13}, /* EMPI */
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{144, 8, 0, 8, 0, 13}, /* MAFE */
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{148, 8, 4, 8, 4, 13}, /* PWM */
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{152, 8, 8, 8, 8, 13}, /* SSC1 */
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{156, 8, 12, 8, 12, 13}, /* IO_PIO1 */
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{160, 8, 16, 8, 16, 13}, /* USB target */
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{164, 8, 20, 8, 20, 13}, /* UART1 */
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{168, 8, 24, 8, 24, 13}, /* Teletext */
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{172, 8, 28, 8, 28, 13}, /* VideoSync VTG */
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{173, 8, 28, 8, 29, 13}, /* VideoSync DVP0 */
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{174, 8, 28, 8, 30, 13}, /* VideoSync DVP1 */
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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/*
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* SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
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*/
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/* INTPRIO0 | INTMSK0 */
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{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
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{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
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{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
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{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
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/* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
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/* INTPRIO4 | INTMSK0 */
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{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
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{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
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{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
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{59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
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{60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
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{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
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{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
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{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
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/* INTPRIO8 | INTMSK0 */
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{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
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{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
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{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
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{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
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{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
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{65, 8, 24, 0, 16, 3}, /* LCDC */
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/* 66, 67 unused */
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{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
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{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
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{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
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/* 71 unused */
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{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
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{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
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{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
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{75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
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{76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
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{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
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{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
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{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
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/* | INTMSK4 */
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{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
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{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
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{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
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{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
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{84, 8, 0, 4, 19, 3}, /* HSPII */
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/* INTPRIOC | INTMSK4 */
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/* 85-87 unused/reserved */
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{88, 12, 20, 4, 18, 3}, /* MMCI0 */
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{89, 12, 20, 4, 17, 3}, /* MMCI1 */
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{90, 12, 20, 4, 16, 3}, /* MMCI2 */
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{91, 12, 20, 4, 15, 3}, /* MMCI3 */
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{92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
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/* 93-107 reserved/undocumented */
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{108,12, 4, 4, 1, 3}, /* ADC */
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{109,12, 0, 4, 0, 3}, /* CMTI */
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/* 110-111 reserved/unused */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2},
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{ 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
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{ PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
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{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
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{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
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{ PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
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#endif
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};
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void __init init_IRQ_intc2(void)
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void make_intc2_irq(struct intc2_data *table, unsigned int nr_irqs)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
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make_intc2_irq(intc2_irq_table + i);
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for (i = 0; i < nr_irqs; i++) {
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unsigned long ipr, flags;
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struct intc2_data *p = table + i;
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disable_irq_nosync(p->irq);
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/* Set the priority level */
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local_irq_save(flags);
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ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET +
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p->ipr_offset);
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ipr &= ~(0xf << p->ipr_shift);
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ipr |= p->priority << p->ipr_shift;
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ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET +
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p->ipr_offset);
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local_irq_restore(flags);
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set_irq_chip_and_handler_name(p->irq, &intc2_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data(p->irq, p);
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enable_intc2_irq(p->irq);
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}
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}
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@@ -51,3 +51,66 @@ static int __init sh7760_devices_setup(void)
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ARRAY_SIZE(sh7760_devices));
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}
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__initcall(sh7760_devices_setup);
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/*
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* SH7760 INTC2-Style interrupts, vectors IRQ48-111 INTEVT 0x800-0xFE0
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*/
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static struct intc2_data intc2_irq_table[] = {
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/* INTPRIO0 | INTMSK0 */
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{48, 0, 28, 0, 31, 3}, /* IRQ 4 */
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{49, 0, 24, 0, 30, 3}, /* IRQ 3 */
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{50, 0, 20, 0, 29, 3}, /* IRQ 2 */
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{51, 0, 16, 0, 28, 3}, /* IRQ 1 */
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/* 52-55 (INTEVT 0x880-0x8E0) unused/reserved */
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/* INTPRIO4 | INTMSK0 */
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{56, 4, 28, 0, 25, 3}, /* HCAN2_CHAN0 */
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{57, 4, 24, 0, 24, 3}, /* HCAN2_CHAN1 */
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{58, 4, 20, 0, 23, 3}, /* I2S_CHAN0 */
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{59, 4, 16, 0, 22, 3}, /* I2S_CHAN1 */
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{60, 4, 12, 0, 21, 3}, /* AC97_CHAN0 */
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{61, 4, 8, 0, 20, 3}, /* AC97_CHAN1 */
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{62, 4, 4, 0, 19, 3}, /* I2C_CHAN0 */
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{63, 4, 0, 0, 18, 3}, /* I2C_CHAN1 */
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/* INTPRIO8 | INTMSK0 */
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{52, 8, 16, 0, 11, 3}, /* SCIF0_ERI_IRQ */
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{53, 8, 16, 0, 10, 3}, /* SCIF0_RXI_IRQ */
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{54, 8, 16, 0, 9, 3}, /* SCIF0_BRI_IRQ */
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{55, 8, 16, 0, 8, 3}, /* SCIF0_TXI_IRQ */
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{64, 8, 28, 0, 17, 3}, /* USBHI_IRQ */
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{65, 8, 24, 0, 16, 3}, /* LCDC */
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/* 66, 67 unused */
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{68, 8, 20, 0, 14, 13}, /* DMABRGI0_IRQ */
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{69, 8, 20, 0, 13, 13}, /* DMABRGI1_IRQ */
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{70, 8, 20, 0, 12, 13}, /* DMABRGI2_IRQ */
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/* 71 unused */
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{72, 8, 12, 0, 7, 3}, /* SCIF1_ERI_IRQ */
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{73, 8, 12, 0, 6, 3}, /* SCIF1_RXI_IRQ */
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{74, 8, 12, 0, 5, 3}, /* SCIF1_BRI_IRQ */
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{75, 8, 12, 0, 4, 3}, /* SCIF1_TXI_IRQ */
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{76, 8, 8, 0, 3, 3}, /* SCIF2_ERI_IRQ */
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{77, 8, 8, 0, 2, 3}, /* SCIF2_RXI_IRQ */
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{78, 8, 8, 0, 1, 3}, /* SCIF2_BRI_IRQ */
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{79, 8, 8, 0, 0, 3}, /* SCIF2_TXI_IRQ */
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/* | INTMSK4 */
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{80, 8, 4, 4, 23, 3}, /* SIM_ERI */
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{81, 8, 4, 4, 22, 3}, /* SIM_RXI */
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{82, 8, 4, 4, 21, 3}, /* SIM_TXI */
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{83, 8, 4, 4, 20, 3}, /* SIM_TEI */
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{84, 8, 0, 4, 19, 3}, /* HSPII */
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/* INTPRIOC | INTMSK4 */
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/* 85-87 unused/reserved */
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{88, 12, 20, 4, 18, 3}, /* MMCI0 */
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{89, 12, 20, 4, 17, 3}, /* MMCI1 */
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{90, 12, 20, 4, 16, 3}, /* MMCI2 */
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{91, 12, 20, 4, 15, 3}, /* MMCI3 */
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{92, 12, 12, 4, 6, 3}, /* MFI (unsure, bug? in my 7760 manual*/
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/* 93-107 reserved/undocumented */
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{108,12, 4, 4, 1, 3}, /* ADC */
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{109,12, 0, 4, 0, 3}, /* CMTI */
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/* 110-111 reserved/unused */
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};
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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}
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@@ -77,3 +77,30 @@ static int __init sh7780_devices_setup(void)
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ARRAY_SIZE(sh7780_devices));
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}
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__initcall(sh7780_devices_setup);
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static struct intc2_data intc2_irq_table[] = {
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{ TIMER_IRQ, 0, 24, 0, INTC_TMU0_MSK, 2 },
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{ 21, 1, 0, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 22, 1, 1, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ 23, 1, 2, 0, INTC_RTC_MSK, TIMER_PRIORITY },
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{ SCIF0_ERI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, 8, 24, 0, INTC_SCIF0_MSK, SCIF0_PRIORITY },
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{ SCIF1_ERI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_RXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_BRI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ SCIF1_TXI_IRQ, 8, 16, 0, INTC_SCIF1_MSK, SCIF1_PRIORITY },
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{ PCIC0_IRQ, 0x10, 8, 0, INTC_PCIC0_MSK, PCIC0_PRIORITY },
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{ PCIC1_IRQ, 0x10, 0, 0, INTC_PCIC1_MSK, PCIC1_PRIORITY },
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{ PCIC2_IRQ, 0x14, 24, 0, INTC_PCIC2_MSK, PCIC2_PRIORITY },
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{ PCIC3_IRQ, 0x14, 16, 0, INTC_PCIC3_MSK, PCIC3_PRIORITY },
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{ PCIC4_IRQ, 0x14, 8, 0, INTC_PCIC4_MSK, PCIC4_PRIORITY },
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};
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void __init init_IRQ_intc2(void)
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{
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make_intc2_irq(intc2_irq_table, ARRAY_SIZE(intc2_irq_table));
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}
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