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mtd: sh_flctl: Restructure the hardware ECC handling

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There are multiple reasons for a rewrite:
 - a race exists: when _4ECCEND is set, _4ECCFA may become true too
   meanwhile, which is lost and a non-correctable error is treated as
   correctable.
 - the ECC statistics don't get properly propagated to the base code.
 - empty pages would get marked as corrupted

The rewrite resolves the issues and I hope it gives a more explicit
code flow structure.

Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Bastian Hecht
2012-05-14 14:14:46 +02:00
committed by David Woodhouse
parent 623c55caa3
commit 6667a6d58e
2 changed files with 87 additions and 42 deletions
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10
include/linux/mtd/sh_flctl.h
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@@ -129,9 +129,15 @@
#define _4ECCEND (0x1 << 1) /* 4 symbols end */
#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
#define INIT_FL4ECCRESULT_VAL 0x03FF03FF
#define LOOP_TIMEOUT_MAX 0x00010000
enum flctl_ecc_res_t {
FL_SUCCESS,
FL_REPAIRABLE,
FL_ERROR,
FL_TIMEOUT
};
struct sh_flctl {
struct mtd_info mtd;
struct nand_chip chip;
@@ -151,8 +157,6 @@ struct sh_flctl {
uint32_t flcmncr_base; /* base value of FLCMNCR */
uint32_t flintdmacr_base; /* irq enable bits */
int hwecc_cant_correct[4];
unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */