firmware: qcom_scm: Order functions, definitions by service/command
Definitions throughout qcom_scm are loosely grouped and loosely ordered. Sort all the functions/definitions by service ID/command ID to improve sanity when needing to add new functionality to this driver. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-16-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Elliot Berman
committed by
Bjorn Andersson
Bjorn Andersson
parent
59b6cf3046
commit
65f0c90b7d
@@ -4,56 +4,27 @@
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#ifndef __QCOM_SCM_INT_H
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#define __QCOM_SCM_INT_H
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#define QCOM_SCM_SVC_BOOT 0x1
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#define QCOM_SCM_BOOT_SET_ADDR 0x1
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0xa
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extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
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extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
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#define QCOM_SCM_SVC_BOOT 0x01
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#define QCOM_SCM_BOOT_SET_ADDR 0x01
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#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
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extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus);
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extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus);
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#define QCOM_SCM_BOOT_TERMINATE_PC 0x2
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags);
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extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
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extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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#define QCOM_SCM_SVC_IO 0x5
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#define QCOM_SCM_IO_READ 0x1
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#define QCOM_SCM_IO_WRITE 0x2
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extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
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extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
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#define QCOM_SCM_SVC_INFO 0x6
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#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x1
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extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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u32 cmd_id);
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_HDCP_INVOKE 0x01
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extern int __qcom_scm_hdcp_req(struct device *dev,
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struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
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extern void __qcom_scm_init(void);
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#define QCOM_SCM_SVC_OCMEM 0xf
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#define QCOM_SCM_OCMEM_LOCK_CMD 0x1
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#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2
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extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
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u32 size, u32 mode);
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extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
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u32 size);
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#define QCOM_SCM_SVC_PIL 0x2
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x1
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x2
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x5
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x6
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x7
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0xa
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#define QCOM_SCM_SVC_PIL 0x02
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
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extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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dma_addr_t metadata_phys);
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@@ -63,6 +34,54 @@ extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
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#define QCOM_SCM_SVC_IO 0x05
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#define QCOM_SCM_IO_READ 0x01
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#define QCOM_SCM_IO_WRITE 0x02
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extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
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extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
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#define QCOM_SCM_SVC_INFO 0x06
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#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
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extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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u32 cmd_id);
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#define QCOM_SCM_SVC_MP 0x0c
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#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
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#define QCOM_SCM_MP_ASSIGN 0x16
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extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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u32 spare);
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extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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size_t *size);
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extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
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u32 size, u32 spare);
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extern int __qcom_scm_assign_mem(struct device *dev,
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phys_addr_t mem_region, size_t mem_sz,
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phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz);
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#define QCOM_SCM_SVC_OCMEM 0x0f
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#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
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#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
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extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
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u32 size, u32 mode);
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extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
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u32 size);
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_HDCP_INVOKE 0x01
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extern int __qcom_scm_hdcp_req(struct device *dev,
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struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
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#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
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extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
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bool enable);
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extern void __qcom_scm_init(void);
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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@@ -90,25 +109,4 @@ static inline int qcom_scm_remap_error(int err)
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return -EINVAL;
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}
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#define QCOM_SCM_SVC_MP 0xc
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#define QCOM_SCM_MP_RESTORE_SEC_CFG 2
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extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
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u32 spare);
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 3
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 4
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#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x3
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x2
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extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
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size_t *size);
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extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
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u32 size, u32 spare);
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extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
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bool enable);
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#define QCOM_SCM_MP_ASSIGN 0x16
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extern int __qcom_scm_assign_mem(struct device *dev,
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phys_addr_t mem_region, size_t mem_sz,
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phys_addr_t src, size_t src_sz,
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phys_addr_t dest, size_t dest_sz);
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#endif
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