Merge drm/drm-next into drm-misc-next
4.19 is out, Lyude asked for a backmerge, and it's been a while. All very good reasons on their own :-) Signed-off-by: Sean Paul <seanpaul@chromium.org>
This commit is contained in:
Sean Paul
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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|
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Copyright (C) 2013-2018 by the following authors:
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||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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@@ -132,14 +132,14 @@ reset_set(void *data, u64 val)
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if (a5xx_gpu->pm4_bo) {
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if (a5xx_gpu->pm4_iova)
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msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->aspace);
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drm_gem_object_unreference(a5xx_gpu->pm4_bo);
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drm_gem_object_put(a5xx_gpu->pm4_bo);
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a5xx_gpu->pm4_bo = NULL;
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}
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if (a5xx_gpu->pfp_bo) {
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if (a5xx_gpu->pfp_iova)
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msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->aspace);
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drm_gem_object_unreference(a5xx_gpu->pfp_bo);
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drm_gem_object_put(a5xx_gpu->pfp_bo);
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a5xx_gpu->pfp_bo = NULL;
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}
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@@ -1231,7 +1231,7 @@ static void a5xx_crashdumper_free(struct msm_gpu *gpu,
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msm_gem_put_iova(dumper->bo, gpu->aspace);
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msm_gem_put_vaddr(dumper->bo);
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drm_gem_object_unreference(dumper->bo);
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drm_gem_object_put(dumper->bo);
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}
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static int a5xx_crashdumper_run(struct msm_gpu *gpu,
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@@ -1433,12 +1433,22 @@ static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu)
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return a5xx_gpu->cur_ring;
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}
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static int a5xx_gpu_busy(struct msm_gpu *gpu, uint64_t *value)
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static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu)
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{
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*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
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REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
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u64 busy_cycles, busy_time;
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return 0;
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busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
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REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
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busy_time = busy_cycles - gpu->devfreq.busy_cycles;
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do_div(busy_time, clk_get_rate(gpu->core_clk) / 1000000);
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gpu->devfreq.busy_cycles = busy_cycles;
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if (WARN_ON(busy_time > ~0LU))
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return ~0LU;
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return (unsigned long)busy_time;
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}
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static const struct adreno_gpu_funcs funcs = {
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@@ -323,7 +323,7 @@ err:
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if (a5xx_gpu->gpmu_iova)
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msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
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if (a5xx_gpu->gpmu_bo)
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drm_gem_object_unreference(a5xx_gpu->gpmu_bo);
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drm_gem_object_put(a5xx_gpu->gpmu_bo);
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a5xx_gpu->gpmu_bo = NULL;
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a5xx_gpu->gpmu_iova = 0;
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@@ -208,6 +208,13 @@ void a5xx_preempt_hw_init(struct msm_gpu *gpu)
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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int i;
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/* Always come up on rb 0 */
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a5xx_gpu->cur_ring = gpu->rb[0];
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/* No preemption if we only have one ring */
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if (gpu->nr_rings == 1)
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return;
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for (i = 0; i < gpu->nr_rings; i++) {
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a5xx_gpu->preempt[i]->wptr = 0;
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a5xx_gpu->preempt[i]->rptr = 0;
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@@ -220,9 +227,6 @@ void a5xx_preempt_hw_init(struct msm_gpu *gpu)
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/* Reset the preemption state */
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set_preempt_state(a5xx_gpu, PREEMPT_NONE);
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/* Always come up on rb 0 */
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a5xx_gpu->cur_ring = gpu->rb[0];
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}
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static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu,
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@@ -272,7 +276,7 @@ void a5xx_preempt_fini(struct msm_gpu *gpu)
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if (a5xx_gpu->preempt_iova[i])
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msm_gem_put_iova(a5xx_gpu->preempt_bo[i], gpu->aspace);
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drm_gem_object_unreference(a5xx_gpu->preempt_bo[i]);
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drm_gem_object_put(a5xx_gpu->preempt_bo[i]);
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a5xx_gpu->preempt_bo[i] = NULL;
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}
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}
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تفاوت فایلی نمایش داده نمی شود زیرا این فایل بسیار بزرگ است
Diff را بارگزاری کن
@@ -2,7 +2,6 @@
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/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
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|
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/pm_opp.h>
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#include <soc/qcom/cmd-db.h>
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@@ -42,9 +41,6 @@ static irqreturn_t a6xx_hfi_irq(int irq, void *data)
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status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
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gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
|
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|
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if (status & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ)
|
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tasklet_schedule(&gmu->hfi_tasklet);
|
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|
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if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
|
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dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
|
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|
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@@ -65,12 +61,14 @@ static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
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A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
|
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}
|
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|
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static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
|
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static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
|
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{
|
||||
int ret;
|
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|
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gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
|
||||
|
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gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
|
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((index << 24) & 0xff) | (3 & 0xf));
|
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((3 & 0xf) << 28) | index);
|
||||
|
||||
/*
|
||||
* Send an invalid index as a vote for the bus bandwidth and let the
|
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@@ -82,7 +80,37 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
|
||||
a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
|
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a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
|
||||
|
||||
return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
|
||||
ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
|
||||
if (ret)
|
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dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
|
||||
|
||||
gmu->freq = gmu->gpu_freqs[index];
|
||||
}
|
||||
|
||||
void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
u32 perf_index = 0;
|
||||
|
||||
if (freq == gmu->freq)
|
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return;
|
||||
|
||||
for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
|
||||
if (freq == gmu->gpu_freqs[perf_index])
|
||||
break;
|
||||
|
||||
__a6xx_gmu_set_freq(gmu, perf_index);
|
||||
}
|
||||
|
||||
unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
|
||||
return gmu->freq;
|
||||
}
|
||||
|
||||
static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
|
||||
@@ -135,9 +163,6 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
gmu_rmw(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK,
|
||||
A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 0);
|
||||
|
||||
gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
|
||||
|
||||
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
|
||||
@@ -348,8 +373,23 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
|
||||
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
|
||||
}
|
||||
|
||||
static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
|
||||
{
|
||||
return msm_writel(value, ptr + (offset << 2));
|
||||
}
|
||||
|
||||
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
|
||||
const char *name);
|
||||
|
||||
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(gmu->dev);
|
||||
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
|
||||
void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
|
||||
|
||||
if (!pdcptr || !seqptr)
|
||||
goto err;
|
||||
|
||||
/* Disable SDE clock gating */
|
||||
gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
|
||||
|
||||
@@ -374,44 +414,48 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
|
||||
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
|
||||
|
||||
/* Load PDC sequencer uCode for power up and power down sequence */
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
|
||||
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
|
||||
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
|
||||
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
|
||||
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
|
||||
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
|
||||
|
||||
/* Set TCS commands used by PDC sequence for low power modes */
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
|
||||
|
||||
/* Setup GPU PDC */
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
|
||||
pdc_write(gmu, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
|
||||
pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
|
||||
|
||||
/* ensure no writes happen before the uCode is fully written */
|
||||
wmb();
|
||||
|
||||
err:
|
||||
devm_iounmap(gmu->dev, pdcptr);
|
||||
devm_iounmap(gmu->dev, seqptr);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -547,8 +591,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
|
||||
}
|
||||
|
||||
#define A6XX_HFI_IRQ_MASK \
|
||||
(A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ | \
|
||||
A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
|
||||
(A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
|
||||
|
||||
#define A6XX_GMU_IRQ_MASK \
|
||||
(A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
|
||||
@@ -626,7 +669,7 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
|
||||
ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT);
|
||||
|
||||
/* Set the GPU back to the highest power frequency */
|
||||
a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
|
||||
__a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
|
||||
|
||||
out:
|
||||
if (ret)
|
||||
@@ -665,7 +708,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
|
||||
ret = a6xx_hfi_start(gmu, status);
|
||||
|
||||
/* Set the GPU to the highest power frequency */
|
||||
a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
|
||||
__a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1);
|
||||
|
||||
out:
|
||||
/* Make sure to turn off the boot OOB request on error */
|
||||
@@ -1140,7 +1183,7 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
|
||||
|
||||
gmu->dev = &pdev->dev;
|
||||
|
||||
of_dma_configure(gmu->dev, node, false);
|
||||
of_dma_configure(gmu->dev, node, true);
|
||||
|
||||
/* Fow now, don't do anything fancy until we get our feet under us */
|
||||
gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
|
||||
@@ -1170,11 +1213,7 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
|
||||
|
||||
/* Map the GMU registers */
|
||||
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
|
||||
|
||||
/* Map the GPU power domain controller registers */
|
||||
gmu->pdc_mmio = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
|
||||
|
||||
if (IS_ERR(gmu->mmio) || IS_ERR(gmu->pdc_mmio))
|
||||
if (IS_ERR(gmu->mmio))
|
||||
goto err;
|
||||
|
||||
/* Get the HFI and GMU interrupts */
|
||||
@@ -1184,9 +1223,6 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
|
||||
if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
|
||||
goto err;
|
||||
|
||||
/* Set up a tasklet to handle GMU HFI responses */
|
||||
tasklet_init(&gmu->hfi_tasklet, a6xx_hfi_task, (unsigned long) gmu);
|
||||
|
||||
/* Get the power levels for the GMU and GPU */
|
||||
a6xx_gmu_pwrlevels_probe(gmu);
|
||||
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#ifndef _A6XX_GMU_H_
|
||||
#define _A6XX_GMU_H_
|
||||
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include "msm_drv.h"
|
||||
#include "a6xx_hfi.h"
|
||||
@@ -47,7 +48,6 @@ struct a6xx_gmu {
|
||||
struct device *dev;
|
||||
|
||||
void * __iomem mmio;
|
||||
void * __iomem pdc_mmio;
|
||||
|
||||
int hfi_irq;
|
||||
int gmu_irq;
|
||||
@@ -74,6 +74,8 @@ struct a6xx_gmu {
|
||||
unsigned long gmu_freqs[4];
|
||||
u32 cx_arc_votes[4];
|
||||
|
||||
unsigned long freq;
|
||||
|
||||
struct a6xx_hfi_queue queues[2];
|
||||
|
||||
struct tasklet_struct hfi_tasklet;
|
||||
@@ -89,11 +91,6 @@ static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
|
||||
return msm_writel(value, gmu->mmio + (offset << 2));
|
||||
}
|
||||
|
||||
static inline void pdc_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
|
||||
{
|
||||
return msm_writel(value, gmu->pdc_mmio + (offset << 2));
|
||||
}
|
||||
|
||||
static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
|
||||
{
|
||||
u32 val = gmu_read(gmu, reg);
|
||||
@@ -103,6 +100,16 @@ static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
|
||||
gmu_write(gmu, reg, val | or);
|
||||
}
|
||||
|
||||
static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
|
||||
{
|
||||
u64 val;
|
||||
|
||||
val = (u64) msm_readl(gmu->mmio + (lo << 2));
|
||||
val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
|
||||
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
|
||||
interval, timeout)
|
||||
@@ -157,6 +164,4 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu);
|
||||
int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
|
||||
void a6xx_hfi_stop(struct a6xx_gmu *gmu);
|
||||
|
||||
void a6xx_hfi_task(unsigned long data);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
@@ -167,8 +167,8 @@ static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_
|
||||
#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000004
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000008
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
|
||||
|
||||
@@ -7,6 +7,8 @@
|
||||
#include "a6xx_gpu.h"
|
||||
#include "a6xx_gmu.xml.h"
|
||||
|
||||
#include <linux/devfreq.h>
|
||||
|
||||
static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
@@ -438,10 +440,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
|
||||
A6XX_PROTECT_RDONLY(0x8d0, 0x23));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(25),
|
||||
A6XX_PROTECT_RDONLY(0x980, 0x4));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(26), A6XX_PROTECT_RW(0xa630, 0x0));
|
||||
gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
|
||||
|
||||
/* Enable interrupts */
|
||||
gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
|
||||
@@ -682,6 +682,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
|
||||
|
||||
gpu->needs_hw_init = true;
|
||||
|
||||
msm_gpu_resume_devfreq(gpu);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -690,6 +692,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
devfreq_suspend_device(gpu->devfreq.devfreq);
|
||||
|
||||
/*
|
||||
* Make sure the GMU is idle before continuing (because some transitions
|
||||
* may use VBIF
|
||||
@@ -744,7 +748,7 @@ static void a6xx_destroy(struct msm_gpu *gpu)
|
||||
if (a6xx_gpu->sqe_bo) {
|
||||
if (a6xx_gpu->sqe_iova)
|
||||
msm_gem_put_iova(a6xx_gpu->sqe_bo, gpu->aspace);
|
||||
drm_gem_object_unreference_unlocked(a6xx_gpu->sqe_bo);
|
||||
drm_gem_object_put_unlocked(a6xx_gpu->sqe_bo);
|
||||
}
|
||||
|
||||
a6xx_gmu_remove(a6xx_gpu);
|
||||
@@ -753,6 +757,27 @@ static void a6xx_destroy(struct msm_gpu *gpu)
|
||||
kfree(a6xx_gpu);
|
||||
}
|
||||
|
||||
static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
u64 busy_cycles, busy_time;
|
||||
|
||||
busy_cycles = gmu_read64(&a6xx_gpu->gmu,
|
||||
REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
|
||||
REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
|
||||
|
||||
busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
|
||||
do_div(busy_time, 192);
|
||||
|
||||
gpu->devfreq.busy_cycles = busy_cycles;
|
||||
|
||||
if (WARN_ON(busy_time > ~0LU))
|
||||
return ~0LU;
|
||||
|
||||
return (unsigned long)busy_time;
|
||||
}
|
||||
|
||||
static const struct adreno_gpu_funcs funcs = {
|
||||
.base = {
|
||||
.get_param = adreno_get_param,
|
||||
@@ -768,6 +793,9 @@ static const struct adreno_gpu_funcs funcs = {
|
||||
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
|
||||
.show = a6xx_show,
|
||||
#endif
|
||||
.gpu_busy = a6xx_gpu_busy,
|
||||
.gpu_get_freq = a6xx_gmu_get_freq,
|
||||
.gpu_set_freq = a6xx_gmu_set_freq,
|
||||
},
|
||||
.get_timestamp = a6xx_get_timestamp,
|
||||
};
|
||||
@@ -799,7 +827,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
||||
}
|
||||
|
||||
/* Check if there is a GMU phandle and set it up */
|
||||
node = of_parse_phandle(pdev->dev.of_node, "gmu", 0);
|
||||
node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
|
||||
|
||||
/* FIXME: How do we gracefully handle this? */
|
||||
BUG_ON(!node);
|
||||
|
||||
@@ -56,5 +56,6 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
|
||||
|
||||
int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
|
||||
void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
|
||||
|
||||
void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq);
|
||||
unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
|
||||
#endif /* __A6XX_GPU_H__ */
|
||||
|
||||
@@ -79,83 +79,72 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct a6xx_hfi_response {
|
||||
u32 id;
|
||||
u32 seqnum;
|
||||
struct list_head node;
|
||||
struct completion complete;
|
||||
|
||||
u32 error;
|
||||
u32 payload[16];
|
||||
};
|
||||
|
||||
/*
|
||||
* Incoming HFI ack messages can come in out of order so we need to store all
|
||||
* the pending messages on a list until they are handled.
|
||||
*/
|
||||
static spinlock_t hfi_ack_lock = __SPIN_LOCK_UNLOCKED(message_lock);
|
||||
static LIST_HEAD(hfi_ack_list);
|
||||
|
||||
static void a6xx_hfi_handle_ack(struct a6xx_gmu *gmu,
|
||||
struct a6xx_hfi_msg_response *msg)
|
||||
static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum,
|
||||
u32 *payload, u32 payload_size)
|
||||
{
|
||||
struct a6xx_hfi_response *resp;
|
||||
u32 id, seqnum;
|
||||
|
||||
/* msg->ret_header contains the header of the message being acked */
|
||||
id = HFI_HEADER_ID(msg->ret_header);
|
||||
seqnum = HFI_HEADER_SEQNUM(msg->ret_header);
|
||||
|
||||
spin_lock(&hfi_ack_lock);
|
||||
list_for_each_entry(resp, &hfi_ack_list, node) {
|
||||
if (resp->id == id && resp->seqnum == seqnum) {
|
||||
resp->error = msg->error;
|
||||
memcpy(resp->payload, msg->payload,
|
||||
sizeof(resp->payload));
|
||||
|
||||
complete(&resp->complete);
|
||||
spin_unlock(&hfi_ack_lock);
|
||||
return;
|
||||
}
|
||||
}
|
||||
spin_unlock(&hfi_ack_lock);
|
||||
|
||||
dev_err(gmu->dev, "Nobody was waiting for HFI message %d\n", seqnum);
|
||||
}
|
||||
|
||||
static void a6xx_hfi_handle_error(struct a6xx_gmu *gmu,
|
||||
struct a6xx_hfi_msg_response *msg)
|
||||
{
|
||||
struct a6xx_hfi_msg_error *error = (struct a6xx_hfi_msg_error *) msg;
|
||||
|
||||
dev_err(gmu->dev, "GMU firmware error %d\n", error->code);
|
||||
}
|
||||
|
||||
void a6xx_hfi_task(unsigned long data)
|
||||
{
|
||||
struct a6xx_gmu *gmu = (struct a6xx_gmu *) data;
|
||||
struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE];
|
||||
struct a6xx_hfi_msg_response resp;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
/* Wait for a response */
|
||||
ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
|
||||
val & A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ, 100, 5000);
|
||||
|
||||
if (ret) {
|
||||
dev_err(gmu->dev,
|
||||
"Message %s id %d timed out waiting for response\n",
|
||||
a6xx_hfi_msg_id[id], seqnum);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
/* Clear the interrupt */
|
||||
gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR,
|
||||
A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ);
|
||||
|
||||
for (;;) {
|
||||
u32 id;
|
||||
int ret = a6xx_hfi_queue_read(queue, (u32 *) &resp,
|
||||
struct a6xx_hfi_msg_response resp;
|
||||
|
||||
/* Get the next packet */
|
||||
ret = a6xx_hfi_queue_read(queue, (u32 *) &resp,
|
||||
sizeof(resp) >> 2);
|
||||
|
||||
/* Returns the number of bytes copied or negative on error */
|
||||
if (ret <= 0) {
|
||||
if (ret < 0)
|
||||
dev_err(gmu->dev,
|
||||
"Unable to read the HFI message queue\n");
|
||||
break;
|
||||
/* If the queue is empty our response never made it */
|
||||
if (!ret) {
|
||||
dev_err(gmu->dev,
|
||||
"The HFI response queue is unexpectedly empty\n");
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
id = HFI_HEADER_ID(resp.header);
|
||||
if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) {
|
||||
struct a6xx_hfi_msg_error *error =
|
||||
(struct a6xx_hfi_msg_error *) &resp;
|
||||
|
||||
if (id == HFI_F2H_MSG_ACK)
|
||||
a6xx_hfi_handle_ack(gmu, &resp);
|
||||
else if (id == HFI_F2H_MSG_ERROR)
|
||||
a6xx_hfi_handle_error(gmu, &resp);
|
||||
dev_err(gmu->dev, "GMU firmware error %d\n",
|
||||
error->code);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (seqnum != HFI_HEADER_SEQNUM(resp.ret_header)) {
|
||||
dev_err(gmu->dev,
|
||||
"Unexpected message id %d on the response queue\n",
|
||||
HFI_HEADER_SEQNUM(resp.ret_header));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (resp.error) {
|
||||
dev_err(gmu->dev,
|
||||
"Message %s id %d returned error %d\n",
|
||||
a6xx_hfi_msg_id[id], seqnum, resp.error);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* All is well, copy over the buffer */
|
||||
if (payload && payload_size)
|
||||
memcpy(payload, resp.payload,
|
||||
min_t(u32, payload_size, sizeof(resp.payload)));
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -163,7 +152,6 @@ static int a6xx_hfi_send_msg(struct a6xx_gmu *gmu, int id,
|
||||
void *data, u32 size, u32 *payload, u32 payload_size)
|
||||
{
|
||||
struct a6xx_hfi_queue *queue = &gmu->queues[HFI_COMMAND_QUEUE];
|
||||
struct a6xx_hfi_response resp = { 0 };
|
||||
int ret, dwords = size >> 2;
|
||||
u32 seqnum;
|
||||
|
||||
@@ -173,53 +161,14 @@ static int a6xx_hfi_send_msg(struct a6xx_gmu *gmu, int id,
|
||||
*((u32 *) data) = (seqnum << 20) | (HFI_MSG_CMD << 16) |
|
||||
(dwords << 8) | id;
|
||||
|
||||
init_completion(&resp.complete);
|
||||
resp.id = id;
|
||||
resp.seqnum = seqnum;
|
||||
|
||||
spin_lock_bh(&hfi_ack_lock);
|
||||
list_add_tail(&resp.node, &hfi_ack_list);
|
||||
spin_unlock_bh(&hfi_ack_lock);
|
||||
|
||||
ret = a6xx_hfi_queue_write(gmu, queue, data, dwords);
|
||||
if (ret) {
|
||||
dev_err(gmu->dev, "Unable to send message %s id %d\n",
|
||||
a6xx_hfi_msg_id[id], seqnum);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Wait up to 5 seconds for the response */
|
||||
ret = wait_for_completion_timeout(&resp.complete,
|
||||
msecs_to_jiffies(5000));
|
||||
if (!ret) {
|
||||
dev_err(gmu->dev,
|
||||
"Message %s id %d timed out waiting for response\n",
|
||||
a6xx_hfi_msg_id[id], seqnum);
|
||||
ret = -ETIMEDOUT;
|
||||
} else
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
spin_lock_bh(&hfi_ack_lock);
|
||||
list_del(&resp.node);
|
||||
spin_unlock_bh(&hfi_ack_lock);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (resp.error) {
|
||||
dev_err(gmu->dev, "Message %s id %d returned error %d\n",
|
||||
a6xx_hfi_msg_id[id], seqnum, resp.error);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (payload && payload_size) {
|
||||
int copy = min_t(u32, payload_size, sizeof(resp.payload));
|
||||
|
||||
memcpy(payload, resp.payload, copy);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return a6xx_hfi_wait_for_ack(gmu, id, seqnum, payload, payload_size);
|
||||
}
|
||||
|
||||
static int a6xx_hfi_send_gmu_init(struct a6xx_gmu *gmu, int boot_state)
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
|
||||
@@ -120,6 +120,7 @@ static const struct adreno_info gpulist[] = {
|
||||
[ADRENO_FW_GMU] = "a630_gmu.bin",
|
||||
},
|
||||
.gmem = SZ_1M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.init = a6xx_gpu_init,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
@@ -237,7 +237,7 @@ enum adreno_pm4_type3_packets {
|
||||
CP_UNK_A6XX_14 = 20,
|
||||
CP_UNK_A6XX_36 = 54,
|
||||
CP_UNK_A6XX_55 = 85,
|
||||
UNK_A6XX_6D = 109,
|
||||
CP_REG_WRITE = 109,
|
||||
};
|
||||
|
||||
enum adreno_state_block {
|
||||
@@ -968,19 +968,19 @@ static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_5 0x00000005
|
||||
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO(uint32_t val)
|
||||
#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK;
|
||||
return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_6 0x00000006
|
||||
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI(uint32_t val)
|
||||
#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK;
|
||||
return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
|
||||
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Block a user