Merge tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/drivers
Qualcomm ARM Based Driver Updates for v4.20 * Refactor of SCM compatibles and clock requirements * SMEM cleanup * Add LLCC EDAC driver * Fixes for GENI clocks and macros * Fix includes for llcc-slice and smem * String overflow fixes for APR and wcnss_ctrl * Fixup for COMPILE_TEST of qcom driver Kconfigs * Cleanup of Kconfig depends of rpmh, smd_rpm, smsm, and smp2p * Add SCM dependencies to SPM and rmtfs-mem * tag 'qcom-drivers-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (38 commits) soc: qcom: geni: geni_se_clk_freq_match() should always accept multiples soc: qcom: geni: Don't ignore clk_round_rate() errors in geni_se_clk_tbl_get() soc: qcom: geni: Make version macros simpler dt-bindings: firmware: scm: Add MSM8998 and SDM845 firmware: qcom: scm: Refactor clock handling dt-bindings: firmware: scm: Refactor compatibles and clocks soc: qcom: smem: a few last cleanups soc: qcom: smem: verify partition host ids match soc: qcom: smem: small change in global entry loop soc: qcom: smem: verify partition offset_free_uncached soc: qcom: smem: verify partition header size soc: qcom: smem: introduce qcom_smem_partition_header() soc: qcom: smem: require order of host ids to match soc: qcom: smem: verify both host ids in partition header soc: qcom: smem: small refactor in qcom_smem_enumerate_partitions() soc: qcom: smem: always ignore partitions with 0 offset or size soc: qcom: smem: initialize region struct only when successful soc: qcom: smem: rename variable in qcom_smem_get_global() drivers: qcom: rpmh-rsc: clear wait_for_compl after use soc: qcom: rmtfs-mem: Validate that scm is available ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@@ -225,19 +225,14 @@ struct geni_se {
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#define HW_VER_MINOR_SHFT 16
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#define HW_VER_STEP_MASK GENMASK(15, 0)
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#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
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#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
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#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
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#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
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u32 geni_se_get_qup_hw_version(struct geni_se *se);
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#define geni_se_get_wrapper_version(se, major, minor, step) do { \
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u32 ver; \
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\
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ver = geni_se_get_qup_hw_version(se); \
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major = (ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; \
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minor = (ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; \
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step = version & HW_VER_STEP_MASK; \
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} while (0)
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/**
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* geni_se_read_proto() - Read the protocol configured for a serial engine
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* @se: Pointer to the concerned serial engine.
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@@ -70,25 +70,51 @@ struct llcc_slice_config {
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/**
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* llcc_drv_data - Data associated with the llcc driver
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* @regmap: regmap associated with the llcc device
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* @bcast_regmap: regmap associated with llcc broadcast offset
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* @cfg: pointer to the data structure for slice configuration
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* @lock: mutex associated with each slice
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* @cfg_size: size of the config data table
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* @max_slices: max slices as read from device tree
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* @bcast_off: Offset of the broadcast bank
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* @num_banks: Number of llcc banks
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* @bitmap: Bit map to track the active slice ids
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* @offsets: Pointer to the bank offsets array
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* @ecc_irq: interrupt for llcc cache error detection and reporting
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*/
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struct llcc_drv_data {
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struct regmap *regmap;
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struct regmap *bcast_regmap;
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const struct llcc_slice_config *cfg;
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struct mutex lock;
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u32 cfg_size;
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u32 max_slices;
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u32 bcast_off;
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u32 num_banks;
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unsigned long *bitmap;
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u32 *offsets;
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int ecc_irq;
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};
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/**
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* llcc_edac_reg_data - llcc edac registers data for each error type
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* @name: Name of the error
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* @synd_reg: Syndrome register address
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* @count_status_reg: Status register address to read the error count
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* @ways_status_reg: Status register address to read the error ways
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* @reg_cnt: Number of registers
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* @count_mask: Mask value to get the error count
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* @ways_mask: Mask value to get the error ways
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* @count_shift: Shift value to get the error count
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* @ways_shift: Shift value to get the error ways
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*/
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struct llcc_edac_reg_data {
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char *name;
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u64 synd_reg;
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u64 count_status_reg;
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u64 ways_status_reg;
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u32 reg_cnt;
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u32 count_mask;
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u32 ways_mask;
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u8 count_shift;
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u8 ways_shift;
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};
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#if IS_ENABLED(CONFIG_QCOM_LLCC)
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