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arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

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[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dinh Nguyen
2022-01-06 17:53:31 -06:00
committed by Greg Kroah-Hartman
parent c5c8c649fe
commit 6493c6aa8b
1 changed files with 2 additions and 2 deletions
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4
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
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@@ -476,7 +476,7 @@
}; };
usb0: usb@ffb00000 { usb0: usb@ffb00000 {
compatible = "snps,dwc2"; compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb00000 0x40000>; reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>; interrupts = <0 93 4>;
phys = <&usbphy0>; phys = <&usbphy0>;
@@ -489,7 +489,7 @@
}; };
usb1: usb@ffb40000 { usb1: usb@ffb40000 {
compatible = "snps,dwc2"; compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb40000 0x40000>; reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>; interrupts = <0 94 4>;
phys = <&usbphy0>; phys = <&usbphy0>;